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PCA9306: PCA9306 leakage current as standby mode

Thomas Chang15933
Expert 4770 points
Part Number: PCA9306

Dear Team:

Our customer used PCA9306DCTT  the chip to be I2C voltage translator.

Vref1 = 1.8V (Normal)

Vref2 = 3.3V (Standy-by)

When system at S5  (Standby mode) : No1.8V, keep 3.3V，We measured Vref1 leakage voltage around 0.6 to 0.7V:

Customer want to know whether the leakage voltage is normal behavior as this setting condition.

 If yes, how to improve it ? customer leakage voltage criterial <0.4V.

Or do we have pin  to pin solution can avoid the issue?============================================================

Customer do some testing: 
Case(3):  R1441 NOPOP,  no leakage voltage。
 
Case(4): R1441 POP 470K ohm, P1V8b leakage voltage (0.6716v)
 
Case(5):  R1439 R1440(470ohm) NOPOP, P1V8b no leakage voltage
 
Case(6): 把 R1439 R1440(1.2k ohm) POP, P1V8b leakage voltage (0.6537v).
 
Case(7): 把 R1439 R1440(2.12k ohm) POP, P1V8b P1V8b leakage voltage (0.6383v).
  • 0
    TI__Guru 50795 points
    Hi Thomas,

    The leakage voltage at Vref1 is a result of how the device uses Vref1, Vref2, and EN to generate its internal reference voltage. To reduce this when Vref1 is set to high impedance, you could add a pull-down resistor, though this would draw more power from P1V8B when the supply is turned back on.
    What I would recommend instead is to disconnect EN pin from Vref2 and tie the EN pin to P1V8B (the lower reference voltage). This should reduce the voltage your seeing at Vref1. However, this will slightly decrease the response time of the device.

    Let me know if this fixes the problem.

    Regards,
    Eric
  • 0 in reply to Eric Schott1
    TI__Expert 4770 points

    Dear Eric:

    Customer asked more questions as below.

    If we disconnect EN pin from Vref2(P3V3_standby) and tie the EN pin to P1V8B directly..

    Does it will works? because I saw the spec that said “ EN at least 1V higher than Vref1(P1V8B)”…

    I have thought two options, could you help to comment them if they will work and what option you prefer?

    (Note: the reason what we don’t using 1.8V as buffer input directly is due to the Vih level is not enough[usually = 2V]).

  • 0 in reply to Thomas Chang15933
    TI__Guru 50795 points
    Hi Thomas,

    The choice depends on your application. If you disconnect EN from Vref2 and tie EN to P1V8B instead, the device will operate as normal, but with a slightly higher propagation delay. The datasheet specifies "EN at least 1V higher than Vref1" to ensure this delay does not increase. If this system isn't very timing sensitive and has manageable trace lengths, I would recommend this option.

    Alternatively, using a pulldown resistor would cause the system to draw more current and may impact other devices using the same supply, but would allow the device to operate within its specifications.

    Let me know if this makes sense and what you decide.

    Regards,
    Eric
  • 0 in reply to Eric Schott1
    Prodigy 30 points
    Hi Eric,
    I will follow your suggestion to disconnect EN from Vref2, but i will let "P1V8B_PWRGD"(3.3V level) as OD buffer input, and OD buffer output(3.3V Stand-by level, 4.7K PU) will drive 6 PCA9306 EN pin to enable switch when normal 1.8V is ready. Because i still has concern about the requirement "EN at least 1V higher than Vref1" for best translator operation.

    May i have your comment for this modification? Thanks.
  • 0 in reply to Andy Ho
    TI__Guru 50795 points
    Hi Andy,

    "EN at least 1V higher than Vref1"
    This is related to the setup example in the datasheet and is not specific to the device itself. When changing the layout from what is used in the datasheet example, this design requirement can be disregarded.

    Regards,
    Eric
  • 0 in reply to Eric Schott1
    Prodigy 30 points
    Hi Eric,

    Noted, thanks for your reply.
    BTW, do you have concern for my modification? (tie multiple PCA9306 EN pin to OD buffer output, P3V3_STBY level, 4.7K PU)
    Because if we apply EN at 1.8V level and Vref1=1.8V , then the Vgs seems hard to > Vth to enable the switch???
    Sorry to ask many questions, just want to figure it out.
  • 0 in reply to Andy Ho
    TI__Guru 50795 points

    Hi Andy,

    Since the device propagates the LOWs from either side, 1.8V compared to GND will be more than sufficient to enable the switch. However, the smaller magnitude of Vref1 means that the signal will propagate later than if it were tied to Vref2. However, this delay is negligible in most cases as it is on the falling edge of the signal. 

    Does this explanation make sense? I'm not sure exactly what your modifications look like. Are you cycling power to EN? Where is your 4.7k PU in relation to EN and Vref1? Could you provide a figure to help me understand?

    Regards,

    Eric

  • 0 in reply to Eric Schott1
    Prodigy 30 points

    Hi Eric,

    Eric: Where is your 4.7k PU in relation to EN and Vref1?  Could you provide a figure to help me understand?

    ==================================

    Andy0718: Please refer to below figures.

    When system power-off, there is no 1.8V, then PCA9306_P1V8A/B_EN pull low(GND) to disable x6 PCA9306 switch (Hi-Z).

    When system power-on, there is 1.8V ready , then PCA9306_P1V8A/B_EN pull high(P3V3_STBY) to enable x6 PCA9306 switch.

    ==================================

    Please advise if any concerns, thanks.

  • 0 in reply to Andy Ho
    TI__Guru 50795 points
    Hi Andy,

    It looks like PCA9306_P1V8B_EN is being pulled up by P3V3_STB when the OD buffer is high impedance. To provide 1.8V to the EN pin, this could be changed to the P1V8B supply or a voltage divider could be used to provide this voltage from P3V3_STB.

    The EN pin on this device does draw a small amount of current when data is driving the device. To stabilize this input, you may consider decoupling capacitors at these pins and series resistors to ensure the noise doesn't propagate to other devices.

    Other than this, the modifications look good. Let me know if you have any more questions.

    Regards,
    Eric