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UCC21520: About the behavior of UCC21520

Tomoaki Yoshida
Expert 2200 points
Part Number: UCC21520

Hi,

I have three questions.

My customers want to know the behavior of UCC21520 in the next mode from the perspective of FMEA.

#1

The behavior when pulses are input unintentionally at the same time to INA and INB.

The following conditoin as:

 Disable is Low or left open

 DT is left open or programmed with RDT

At this time, either output is instantaneously high for internal propagation delay, after that both output will go Low.

Is it correct?

In that case, please let me know the definition of the time when the output becomes High.

For example, output becomes high due to the propagation delay difference between OUTA and OUTB.

It is assumed if the input is totally simultaneous.

#2

What happens when DT is shorted to GND?

・The dead time will zero but it normally operates

・It will not normally operate.

  for example, the both output keep low.

#3

Is not the NC pin connected to any other internal node in IC?

I would like to know if these NC pins are short-circuited with other nodes externally but there is no problem with IC operation.

It is not assumed that one NC pin can simultaneously short to two nodes, or two NC pins simultaneously short to another node.

Best regards,

Tomoaki Yoshida

  • 0
    Expert 2200 points

    Hi,

    Any update for this issue?

    This information is very important to us.

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida
    TI__Intellectual 2805 points
    Hi Tomoaki,

    I am an applications engineer for this device.

    I have reached out to our design team for your first and second question.

    For your third question, the NC pins are not connected to any other internal node. There are actually no bond wires tied to these pins.

    Regards,
    Mateo
  • 0 in reply to Mateo Begue
    Expert 2200 points

    Hi Mateo-san,

    Thank you for your reply.

    I'm waiting for answer from design team.

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida
    TI__Intellectual 2805 points

    Hello Tomoaki-san,

    For question 1)

    If INA and INB are exactly same, both outputs are always low. (As shown in figure 33 condition E)

    If there are a little ns difference between INA and INB pulses (e.g. INB is lag behind INA), OUTA can see a narrow pulse (basically the time difference between INA and INB), OUTB is always low.

     

    For question 2)
    When shorted to GND, the dead time behaves similarly as when the DT pin is floating: <15-ns.
    We recommend floating the pin instead of connecting it to ground. When connected to ground the quiescent current of the DT block is about 1.34mA larger than DT left floating.

    Thus, we don't recommend to put a small RDT or short for 8-ns dead time since minimum DT can be obtained by floating pin.

     

    If this answered your question, please click the verify button.

     

    regards,

    Mateo




     

  • 0 in reply to Mateo Begue
    Genius 5255 points
    Hi Mateo-san,

    Thank you for your reply.
    I have an additional question about answer 1.

    Is the minimum width of a narrow pulse defined?
    We are asking this question to check the behavior when input is short-circuited in abnormal mode.
    Even if it is input at the same time to the INA and INB pin of the IC, is there a possibility that a narrow pulse of a few nsec will be generated due to internal delay?
    If there is not it, can we think that narrow pulse is not issued if the delay difference of the IC input end is less than a few seconds?


    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Mateo Begue
    Expert 2200 points
    Hi Mateo-san,

    I'm sorry for late reply.

    I have an additional question for answer 1.

    Is the minimum width of the narrow pulse defined?
    We want to check the unintended input terminal short behavior.

    If the delay between INA and INB is less than a few nsec, can it be thought that the pulse does not come out?
    Or, at least due to the internal delay of the IC, should we think pulses of several nsec may be emitted?

    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Tomoaki Yoshida
    TI__Intellectual 2805 points
    Hello Tomoaki-san,

    Yes, the minimum pulse is defined in section 6.10 Switching Characteristics: t_PWmin = 20-ns (MAX).

    There should not be an output pulse in this short-circuit condition.
    If there is a delay been INA and INB, to prevent overshoot INA pulls OUTB low and keeps OUTA low as described in figure 33.

    Regards,
    Mateo
  • 0 in reply to Mateo Begue
    Expert 2200 points

    Hi Mateo-san,

    Thank you for your reply.

    I understood the minimum pulse width.

    Do you mean a narrow pulse will never be output at input short-circuit because DT works to pull OUTB low?
    Which timing shown in Figure 33 is satisfied?
    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Tomoaki Yoshida
    Genius 5255 points
    Hi Mateo-san,

    Is there any update on this issue?

    I'm looking forward to your reply.

    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Tomoaki Yoshida91
    TI__Genius 12990 points
    Hi Tomoaki-san,

    Sorry for the late reply our team is querying the designer for an exact answer for minimum width of a narrow pulse.

    Thanks for your patience.
  • 0 in reply to Jeffrey Mueller
    TI__Genius 12990 points
    Hi Tomoaki-san,

    Just wanted to update you, I am still working on an answer for you. I could test this out myself however there would be some margin of error from part to part so I am trying to find the right person to assist with this. Stay tuned!

    Thanks
  • 0 in reply to Jeffrey Mueller
    Genius 5255 points
    Hi Jeff-san,

    Thank your for your support.
    I'm looking forward to hearing from you.

    Best regards,
    Tomoaki Yoshida
  • 0 in reply to Tomoaki Yoshida91
    TI__Genius 12990 points
    Hi Tomoaki-san,

    After asking around it seems I will need to verify on bench to satisfy your answer.

    If DT is open, outputs overlapping is not allowed.
    This means - if INA and INB go high same time, both outputs are always low.

    If there are a little ns difference between INA and INB pulses (e.g. INB is lag behind INA), OUTA can see a narrow pulse (basically the time difference between INA and INB), OUTB is always low.
    note: a ns difference of (INA and INB) of 5ns or less will be filtered out.

    I will verify this on the bench and update you with the results in 24-48hrs.

    Thanks,
  • 0 in reply to Jeffrey Mueller
    TI__Genius 12990 points

    Hi Tomoaki-san,

    I went to the lab and did some bench testing. I attached my results in a PDF. I did the testing at room temperature with no load. My results show a 15-20ns output pulse.

    I hope this answers your question, please let me know if you have any others.

    Output_Pulse_Bench_Test_UCC2152x.pdf

    Thanks

     

  • 0 in reply to Jeffrey Mueller
    Genius 5255 points

    Hi Jeffery-san,

    Thank you for  your strong support.

    It is very helpful for us.

    I understood that a short pulse of more than 15 - 20 ns is output with an input delay of more than 5ns.

    I know that the INA and INB are short-circuited, the internal delay is sufficiently small even when considering variations.
    So I do not recognize that pulses will be output even at the minimum dead time.

    Is it correct?

    Best regards,

    Tomoaki Yoshida

  • 0 in reply to Tomoaki Yoshida91
    TI__Genius 12990 points

    Hi Tomoaki-san,

    Thank you sir! Im happy to help!

    I dont completely understand your question (PDF#1 is done with minimum DT). I attached a PDF (PDF#2) that shows you how deadtime, delay matching time and propagation delay time are measured to make things clearer.

    DT_propagation delay_delay time_UCC2152x.pdf

    *If simultaneous INA/B occur then the delay matching time (<5ns max) cant be large enough to output a pulse. If you have DT set to minimum deadtime (<=15ns)i.e no overlapping pulses, then an input delay of 10-20ns will give you an output pulse of about 20ns @  8-12V as seen in PDF#1 -> at 5ns input delay you will still get an output pulse however at 3.5V the pulse is small an negligible. PDF#1 also showed that after about 20ns of input delay, the output delay would closely match the input delay and the voltage of the pulse will be closer and closer to VDDA/B.

    **note: the fact that you have deadtime means that you do not want the pulses to overlap -> if pulses overlap then deadtime is 0ns

    ***also note: there are two deadtimes -> 1) when OUTA falls and OUTB rises -> 2) when OUTB falls OUTA rises (uses input DT if input DT is longer) -> see screenshot below

    I hope this answers your question, please let me know if I didnt!

    Thanks,

  • 0 in reply to Jeffrey Mueller
    TI__Genius 12990 points

    The screenshot was deleted somehow. I attached it here.