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TMS320F28035: When SCI Transmit FIFO is empty, how long does the FIFO interrupt actives？

F.F
Genius 3095 points
Part Number: TMS320F28035

Hi all

I'm using F28035，enable SCI Transmit FIFO interrupt (TXFFIENA=1), and set TXFFIL=0 (Transmit FIFO interrupt level bits). 

Some times when run into Transmit FIFO interrupt ISR, I get no data to write to the TX FIFO ( thus the TX FIFO is empty for a long time), and I find the ISR will active continuously (this mode works for me), but I do not know how long does the interrupts active between one from another?

Best regards

  • 0
    TI__Genius 17315 points
    F.F.

    The Minimum latency for an Internal interrupt is 14 cycles. (For an external interrupt the minimum latency is 16 cycles.)

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken
  • 0 in reply to Ken Schachter
    TI__Genius 17315 points
    F.F.

    It's been a while since I have heard from you last. Therefore, I am assuming that my last reply resolve your issue. If this isn’t the case, please reject this resolution or reply to this thread. If this thread locks, please make a new thread describing the current status of your issue. Thank you.

    - Ken