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Qustion about EMIF Asynchronous mode operation with FPGA

user1411371
Intellectual 990 points
Other Parts Discussed in Thread: TMS570LS3137

I met some problems in writing and reading EMIF address in asynchronous mode with FPGA.

I set data width 16 bit and, normal mode and in FPGA 1 bit address is 16 bit data.

As show in the figure, I can only use address even bits like 0x060000040 and 0x06000042.

The odd bits address are always FFFF and the 32 bits data shown like 0x2020FFFF.

And I found that if I set data width in 8 bit mode, the 32 bits data become like 0x20FFFFFF.

24 bits of the data can't be used.

I have question about that I can only use 16 bits of 32 bits data. Is it correct ?

  • 0
    TI__Mastermind 22715 points
    I assume that it is TMS570LS3137 type of device. You will have configure MPU to make EMIF region as device or strongly ordered. Extra WE pulse will be generated if writing asynchronous EMIF in normal mode.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Intellectual 990 points
    The device is RM48L952ZWT, i didn't use MPU in my program ( even not added sys_mpu.asm to the project). And I tried add MPU in EMIF region as device and strongly ordered, it doesn't work. should I check the subregion or anything else ?
    I'll read MPU documents and try it.
  • 0 in reply to user1411371
    TI__Mastermind 22715 points
    Would you please provide more details about "doesn't work"? Did you still see extra WE pulses? If so, the MPU is no configured correctly.

    Thanks and regards,

    Zhaohong
  • 0 in reply to Zhaohong Zhang
    Intellectual 990 points

    This is the MPU setting in HCG ( I'm not sure it's right, if this is wrong , could you help me to fix the setting ? )

    and in main(), I implemented      _mpuInit_() and _mpuEnable_()

    This is the code I operated FPGA by EMIF, you can see half of the content are 0xFFFF and can't be write

    this is the wave that FPGA JTAG Emulator catch, the wave shows address 0x21( in CPU address is 0x60000042) has been written

    but in CCS debugger the memory map shows that 0x60000042 is 0xFFFF,

    FPGA's 0x21 ( CPU's 0x60000040) is right

    I don't know which part is uncorrect, MPU ? EMIF setting ? or FPGA.

    could you help me to analyse this ?

  • 0 in reply to user1411371
    Intellectual 680 points
    You need to decode the proper EMIF address lines in FPGA. For a 16 bit data access you should concatenate A[12:0] with BA[1] to create a 14 bit address where BA[1] is your Address line [0]. Take a look at this answer by Anthony: e2e.ti.com/.../312729.