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What is MSP430F5XXX SMCLK default frequency at Power on?

Hao Hua
Prodigy 70 points

What is MSP430F5XXX SMCLK default frequency at Power on?

I read datasheet of MSP430F5xxx (SLAU208J.PDF).http://www.ti.com/lit/ug/slau208j/slau208j.pdf

Page 382

NOTE: Watchdog timer powers up active.
After a PUC, the WDT_A module is automatically configured in the watchdog mode with an
initial ~32-ms reset interval using the SMCLK. The user must setup or halt the WDT_A prior
to the expiration of the initial reset interval.

Page 136
SELS Bits 6-4 Selects the SMCLK source

The SELS defualt is 100 DCOCLKDIV

Page 135
SELREF Bits 6-4 FLL reference select. These bits select the FLL reference clock source.

The SELREF defulat is  000 XT1CLK


My system have on external osc, only use REFO (32768Hz) to generate 16Mhz.
When mcu boot, if I don't nothing(dont initialize register),don't disable watchdog or reset watchdog,would happen watchdoc time out reset ?????

According the default value (The SELS defualt is 100 DCOCLKDIV.The SELREF defulat is  000 XT1CLK)

I have on external osc, the XT1CLK have no signal.
Power on,SMCLK have on signal,the watchdog would not work.
The system doesn't happen watchdog time out reset, Right????

 

  • 0
    Genius 4925 points

    No, the SMCLK is sourced by DCODIV. The FLL uses XT1CLK to stabilize the DCOCLK to 2.097152 MHz, the SMCLK is DCO/2 so 1.048576 MHz.

    Now even if the FLL has no reference signal the DCO would run at a certain frequency, it will not disable the DCO - just the frequency wouldn't be the above stated values.

    However, the UCS is a bit more intelligent. If the XT1 fault flag is set (no oscillation of XT1 through whatever reason) the FLL reference is automatically switched to REFO oscillator. It then tries to get the above frequencies using the REFO, which has quite some tolerances but you will get a frequency quite close.

    So in the end you will a) always have a watchdog timeout as SMCLK will have a clock signal as the DCO is not turned off and b) even without a XT1 low frequency crystal you will get a roughly 1 MHz SMCLK due to REFO being used as FLL reference.

    See section 5.2.12 UCS Module Fail-Safe Operation (page 128) of the 5xx family user guide (you linked). 

  • 0 in reply to Bernhard Weller
    Prodigy 70 points

    Thanks,

    I will re-read the datasheet again.

     

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