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TMS320C6748: interrupt handling, PRU

Part Number: TMS320C6748
Other Parts Discussed in Thread: OMAPL138

Questions on interrupt control and handling by C6748 DSP:

1.  In the host, how do you map interrupt source to a particular interrupt, e.g. INT5?   Is there a library or template C source code available?

2.  I want to generate an interrupt from PRU to Host core?  In particular, how can I use R31:30 or R31:31 to signal interrupt to Host.  Please explain how to set this up on the host side; there was no matching entry in the

DSP interrupts table.  On the PRU side, I'd suppose I can simply set the bit, correct?

Thank you.

Peter H.

  • Hi Peter,

    Please share which Processor SDK RTOS version are you using? Or which version of TI libraries?

    Best Regards,
    Yordan
  • Bare metal context. No RTOS. Writing C code from scratch.

    How does host recognize Host 0 and Host 1 interrupts?  I was able to find PRU_EVT0 through 7 among interrupt sources recognized by the host, but not Host 0 and Host 1?  How are they handled?

  • Peter,

    Host 0/1 interrupt is actually for PRUs, not targeted to host (DSP) core, see TRM 12.7.1 Introduction:

    -Generation of 10 Host Interrupts
    – 2 Host Interrupts for the PRUs
    – 8 Host Interrupts exported from the PRUSS for signaling the host (ARM/DSP) interrupt controllers

    And details in 12.4.2 Status Mapping (R31): Interrupt Events Input.

    To generate an interrupt from PRU to Host core (DSP), instead of R31:30 or R31:31, please check 12.4.1 Event Out Mapping (R31): PRU System Events, and CHANMAP/HOSTMAP registers need to be set up accordingly per 12.7.2 Interrupt Mapping as well as 12.7.5.10 Configuring the Interrupt Controller.

    In host (DSP) side, refer to 2.2.2.1 Interrupt Controller (INTC), and the APIs in pdk_omapl138_1_0_6\packages\ti\osal\src\nonos\RegisterIntr_nonos.c

    Regards,
    Garrett