0412.Clocking High Speed Data Converters - 3_17_2013.pptx Hassan,
Normally it is not a good idea to use the FPGA as a clock source for the ADC. These clocks usually have poor phase noise which directly effects the performance of the ADC. See attached document…
Mahmoud,
Most of our newer high speed ADC use clock device from the LMK family, such as the LM04828. You will need to figure out how much SNR performance you need out of the ADC. From this, you can figure out the jitter requirements of the clock source…
User,
SYSREF has nothing to do with jitter. This is only used to synchronize multiple devices. The input clock divider allows more flexibility for system clock architecture design. This will not help with jitter.
SYSREF only works if CLK DIV is set to…
Clocking High Speed Data Converters - 3_17_2013.pptx Shivakant,
Please see the attached document regarding your jitter question. Basically, the less jitter, the better the performance. This document will show you how to calculate the ADC performance based…
Manos,
Contact the clocking forum regarding the pll questions of the LMX device. See if the attached documents help regarding your other questions.
Regards,
Jim
2352.Clocking High Speed Data Converters - 3_17_2013.pptx 2084.ADC Basics.pdf
5466.Clocking High Speed Data Converters - 3_17_2013.pptx 4666.ADC Basics.pdf Paul,
See section 4.3 of the document titled "ADC Basics". The second document goes into much more detail if needed.
Regards,
Jim
Henry,
The schematic appears to be fine. What is sourcing the clock? SNR is directly related to the phase noise of the clock. If you want better SNR, provide a cleaner clock.
Regards,
Jim
7737.Clocking High Speed Data Converters - 3_17_2013.pptx
Yinon,
Yes, using a 1:N transformer will allow you to increase the signal swing without adding noise as this is a passive device. You will need to be careful when choosing a transformer as the linearity will vary from model to model. I have attached a…
Other Parts Discussed in Thread: ADC16DV160 , ADS5483 Hello Guys
We are designing an ADC FMC card with 4 channels. We intend to prototype two boards, with two different converters, one running at maximum 130 MSPS and other with maximum 250 MSPS, both are16…