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Showing 9 results View by: Thread Post Sort by
  • CDCL1810: I2C programming possible before clock appears on (CLKP, CLKN) input?

    Daniel Nagy96
    Daniel Nagy96
    TI Thinks Resolved
    Part Number: CDCL1810 Dear Forum, The CDCL1810 device defaults to 1:1 frequency division and enabled outputs. However, I would need a different division ratio from the very moment that the chip starts to receive the clock signal on its (CLKP, CLKN) input…
    • over 6 years ago
    • Clock & timing
    • Clock & timing forum
  • RE: LMK04828: Need support for operating LMK04828BISQ as an LVPECL driver

    William Pfennigwerth
    William Pfennigwerth
    Vraj, I am taking over this question while Andrea is out of office. In regards to your original question. Yes, it it is possible to DC couple a LVPECL into your other device. The first place to look as Andrea mentioned is the input requirements for your…
    • over 1 year ago
    • Clock & timing
    • Clock & timing forum
  • RE: LMK1D1208: LMK1D1208RHDT

    William Pfennigwerth
    William Pfennigwerth
    Pat, Note that the datasheet for the LMK00334 does not list CML as an output type. If CML is your desired output you may want to look for a buffer that supports CML outputs such as the CDCL1810 Which inputs I should route to (preferred for best performance…
    • over 1 year ago
    • Clock & timing
    • Clock & timing forum
  • CDCL1810 common mode bias voltage

    Longchang Chen
    Longchang Chen
    Other Parts Discussed in Thread: CDCL1810 Does t he LVDS input of CDCL1810 have the internal common - mode biasing voltage? O r it has to use external bias voltage?
    • over 12 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDCLVP1102: CML Levels

    Noel Fung
    Noel Fung
    Resolved
    Hi Henry, We have two 1:10 buffers that support CML output, they are CDCL1810 and CDCL1810A. If LVPECL output is acceptable, we have CDCLVP1102 which is a 1:2 buffer.
    • over 4 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDC5801A: CDC5801A

    Lane Boyd
    Lane Boyd
    Resolved
    We have some other clock dividers that may fit your needs. Please take a look at our offering here: www.ti.com/.../products.html I recommend looking into LMK01000 and CDCL1810 for low additive jitter. The LMK010x0 family are low-jitter has 8 outputs…
    • over 6 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • RE: CDC318A: CDC318A: Industrial grade option ??

    Arvind Sridhar
    Arvind Sridhar
    Resolved
    Hi Prahlad, I don't believe we have CDC318A in Industrial Grade. You could try CDCL1810, 10-output high-performance clock distributor that supports I2C interface for individual output enable/disable. http://www.ti.com/lit/ds/symlink/cdcl1810.pdf R…
    • over 8 years ago
    • Clock & timing
    • Clock & timing forum
  • Answered
  • Re: Low Jitter clock distribution

    Fritz
    Fritz
    Resolved
    Hello Asad, the CDCM61001 + buffer IC will be a fine solution. You didn't indicate what signaling your inputs require. Is it LVDS, CML, LVPECL, or single-ended? If it's LVDS , you could use the CDCMVD110: http://focus.ti.com/docs/prod/folders…
    • over 14 years ago
    • Clock & timing
    • Clock & timing forum
  • Re: High-speed counter/divider

    Fritz
    Fritz
    Hello Tom, I am not sure I fully comprehend your requirements (it's late here) but let me make a few comments: 1. If you need to generate a 100MHz clock, you could consider using a CDCM61001 with an external 25MHz XTAL or drive it from the TCXO…
    • over 14 years ago
    • Clock & timing
    • Clock & timing forum

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