What is the single-ended LVCMOS signaling level (1.5, 1.8, 2.5, 3.3 V?) you need for your target devices? What supply rails do you prefer or have available for the clocks?
For CLKGEN board, could you use the following?
8.192 MHz XO --> CDCLVC1102 (1:2…
You would just add the max output skew of the CDCLVC1104 (1st buffer stage) and the max part-to-part skew of the CDCLVC1110s (2nd buffer stage).
Worst-case output skew between any 2 outputs of CDCLVC1110s: 50 ps + 0.5 ns = 0.55 ns max (assuming all parts…
Hello Asad,
the CDCM61001 + buffer IC will be a fine solution. You didn't indicate what signaling your inputs require. Is it LVDS, CML, LVPECL, or single-ended?
If it's LVDS , you could use the CDCMVD110: http://focus.ti.com/docs/prod/folders…