Part Number: LMK04828 Other Parts Discussed in Thread: CLOCKDESIGNTOOL , Dears.
We would like to suggest the conditions of PLL1 setting and loop filter design in H / W condition.
I would like to receive recommendations from TI.
H / W condition (OSCin …
My apologies for the delay. Could you try using Clock Design Tool (downloadable here: www.ti.com/.../clockdesigntool) to optimize your LMK03200 design? The design wizard should generate device settings for optimal jitter performance…
You can use the Clock design tool for simulating the phase noise performance. You can download it from the link below:
Let me know if you see any issue using the tool.
The simulatio tool could help you.
For LMK04828, try "CLock Design Tool", www.ti.com/.../clockdesigntool
ForLMX2582, try "pllatinumsim" , www.ti.com/.../pllatinumsim-sw
You could mannually set "CLock Design Tool" output…
The evaluation board users guide for the LMK048xx family of parts: www.ti.com/lit/snau076 has a phase noise plot down to 10 Hz using a VCXO from Crystek
You should be able to simulate LMK04805 output clock phase noise performance using a commercial VCXO…
Do you know if the jitter from the FPGA DCM that causes the occasional video dropout is high-frequency jitter, low-frequency jitter, or both? Have you tried to do jitter analysis/decomposition on the DCM clock that needs cleaning? If you have some jitter…
To emulate PLL2 only, set PLL1 for a very low loop bandwidth like 1 Hz. Soon you should be able to select a theoretical '0 Hz' loop bandwidth filter for PLL1. This will cause the VCXO noise to be dominant and you can load the VCXO with…
The LMK04808 can be used in 0-delay mode for 125 MHz input and output.
The jitter performance can be simulated using the ClockDesignTool or Clock Architect, while it doesn't specifically support a 0-delay configuration in simulation, this does…
Other Parts Discussed in Thread: LMK04906 , CLOCKDESIGNTOOL Hi
We have a question about LMK04906 jitter cleaner.
1. According to the datasheet, LMK04906 offers 115-fs RMS jitter (BW=12KHz- 20Mz).
How to get peak to peak jitter?
2. The 115-fs RMS jitter…
Other Parts Discussed in Thread: CLOCKDESIGNTOOL , LMK04828 It appears the latest ClockDesignTool does not support the LMK04828. When will support be added, or - do you have a suggested work around using a similar device that is supported?