Other Parts Discussed in Thread: LMK04906 , CLOCKDESIGNTOOL Hi
We have a question about LMK04906 jitter cleaner.
1. According to the datasheet, LMK04906 offers 115-fs RMS jitter (BW=12KHz- 20Mz).
How to get peak to peak jitter?
2. The 115-fs RMS jitter…
Other Parts Discussed in Thread: CLOCKDESIGNTOOL Hello,
This seems to be a very useful chip, for me to digest and to use its LVPECL features:
1). What does "jitter cleaner" mean ? ( Does this mean its output jitter is determined by its VCXO…
Other Parts Discussed in Thread: CODELOADER , CLOCKDESIGNTOOL Hi,
Recently we purchased the LMK040xx Evaluation Board, and there is some issue to make this board work. The schematics in the LMK040xx Evaluation Board is not readable.
Can I get the schematics…
Other Parts Discussed in Thread: LMK04808 , CLOCKDESIGNTOOL Hi,
I'm wondering about the lower end frequency for the inputs to LMK04848.
We're using the LMK04808 with dual PLL and internal VCO. PLL1 is set up to compare CLKin0 and CLKin1(FEEDBACK_MUX…
Hi Thom,
Sorry for the late reply yet again!
CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin). The structure of the reference path and input mux is similar between CLKin1 and CLKin0. There is no…
Other Parts Discussed in Thread: CLOCKDESIGNTOOL , LMK04828 It appears the latest ClockDesignTool does not support the LMK04828. When will support be added, or - do you have a suggested work around using a similar device that is supported?
Hello,
I experimented with the tool a bit, and wasn't able to reproduce your problem.
I notice the crash note says v1.3.4. Latest version is v1.3.5.
Perhaps the latest version has no issue? http://www.ti.com/tool/clockdesigntool
73,
Timothy
Other Parts Discussed in Thread: LMK02002 , CLOCKDESIGNTOOL Hello,
My customer wants to generate 1MHz clock by source 1kHz clock.
Which should I select the device in TI's products.
There is no limit of operating voltage.
Regards,
Naoki Aoyama
Dean
For using the function of fast lock, setting FLCPG = 31 but I can not select a Optimozed CPG value.
I am trying to design PLL by using Clock design tool, http://www.ti.com/tool/clockdesigntool.
It helps user have values of loop filter but it does…
Hi Edward,
You might be able to use the LMK04033B device in a configuration as shown below to achieve the desired ADC and DAC frequencies. You could pick a 20 MHz VCXO as shown in the configuration or another common one of your choice. Please use the National…