Part Number: LMK00338 Hi, support team
My customer has the questions as follow:
There is no record of SRIS support or SRnS support in LMK00338‘s datasheet. Can't LMK00338's PCLe support SRIS and SRnS architecture?
Thanks so much.
Best regards…
Part Number: LMK00338 Other Parts Discussed in Thread: CDCDB800 Hi experts
I'm working on a design using LMK00338 and need to determine the minimum Vod in HSCL mode.
The spec table lists min/max Voh and Vol, but doesn't list Vod.
What is the realistic…
Part Number: LMK00338 Hi,
We planned to use LMK00338RTAT PCIe Clock Buffer for our design.
2 Input Clock and 5 Output HCSL Clocks.
We dont need Osc Input and LVCMOS Output.(is there any guidelines for not used pins?)
Please verify the Schematics…
Part Number: LMK00338 Hi team,
Customer mentions that Vcross(Absolute crossing point voltage) of LMK00338 doesn't match with the standards(Refclk DC Specification and AC Timing Requirements Table 8-16 & Table 8-17).
The Vcross of this device is…
Part Number: LMK00338 HI,
What is the expected HCSL output swing level, VOL/VOH level for VCCO=2.5V and VCCO=1.8V? VCC=3.3V.
In the table only show for VCCO=3.3V.
tx
rdgs
stloh
Part Number: LMK00338 Hi team,
As written on the datasheet 8.3.3 Clock Outputs, any unused output pin should be left floating with a minimum copper length (see note below) to minimize capacitance and potential coupling and reduce power consumption…
Part Number: LMK00338 Other Parts Discussed in Thread: LMK00334 Hi team,
My customer is searchingn for a PCIE clock driver which can convert 1 input to 5 output. The input and output clk frequency are all 100MHz. And the input and output logic level…
Part Number: LMK00338 My LMK00338 design is not producing an output signal on any of the outputs. I am enclosing a snapshot of my schematic along with a scope-shot of the input signal (I captured one leg of a differential input). Both voltage rails (3V3_CLK…
Part Number: LMK00301 Other Parts Discussed in Thread: LMK00338 , It looks like both the LMK00301 and LMK00338 meet the additive jitter requirements for PCIe Gen 5 clock distribution, but it isn't specified in the data sheet. Can you confirm the LMK00301…