Hello,
LMK03200 does have a VCO divider block which can be bypassed. The configuration shown in the clock design tool has the VCO divider bypassed.
If you would like to use LMK03200 with VCO divider block (necessary if using 0-delay), then please use…
Other Parts Discussed in Thread: LMK03806 , LMK03000 , LMK02000 Hi,
I'm begginer and have a question about Clock IC.
In TI web page of Clock product there are category of Clock Generator and Clock Jitter Cleaner. http://www.ti.com/lsds/ti/analog/clockandtiming…
Other Parts Discussed in Thread: LMK03000 , LMK03200 LMK03200 & LMK03000 series have no recommendations related to bypassing the 14 VCC pins on the chip in their data sheets. I noticed (from a note on the forum) that LMK04800 series has a nice note discussing…
Hello Praveen,
In the attach PDF I try to show a possible solution for a clock distributions from crystal source through TI LMK03000 and LMK01010 Timing products to the LM96570 and FPGA , plus synchronization Reset implementation .
1385.Reset c.pdf
Other Parts Discussed in Thread: LMH1983 , LMK03000 , CODELOADER We have designed a board with uses a LMH1983 from national and we use this as an input to the LMK03000
We AC coupled the inputs and have a differential swing of 800 mV and a frequentie of 148…
Hi Shanker,
If your application is clock generation, i.e. you have a clean reference clock and want to generate a 100MHz LVPECL clock, you don't need to use dual PLL jitter cleaner like LMK04000. You could simply use clock generators, for example, LMK03000…
Other Parts Discussed in Thread: LMK03000 what is the operation temperature of LMK3000C?
it is very hot on my board and no PLL function appeared !
thanks!
Hi Jie,
Pls note that for LVPECL outputs (CLKout3 to 7), they need pull down bias resistors. Pls refer to LMK03000 datasheet, section 3.7 for details.
Did you mean the VCXO freq chagne periodically? Configure PLL_MUX to "Digital LD Active High" and check…
Hello Ron,
Sorry for your trouble.
Two issues are going on here.
1) The LMK0482x profiles for the CDT does not support the SYSREF divider. So the max divide is 32 which doesn't allow it to find 19.2 MHz.
- A workaround is to put a multiple of this…