Part Number: LMK04000 Hi every one
In my design i am using LMK04000BISE PLL clock conditioner for my ADC input. The problem i am facing right now is that
the clock output (CLKOUT1 AND CLKOUT2) which is configured as output for 125MHz from reference input…
Other Parts Discussed in Thread: LMK04000 Hello,
I want to use the LMK04000 PLL. In the datasheet VOSCin is specified to be 0.2-2Vpp in single ended mode and 0.4-3.1Vpp for differential mode.
On the other hand, the LMK040xx evaluation board uses the CVHD…
Other Parts Discussed in Thread: LMK04000 Hello,
I am using the LMK04000 to clean up a recovery clock source. However I require that the phase relationship between the input clock source and the output frequency be consistent (always the same phase difference…
Hi,
I am using LMK04000BISQE IC in my design. I has 5 clock output among these 5 channels, I am using only second and third clock output port in a single ended CMOS input type.
Remaining three clock output ports are not going to be used. So, through register…
Other Parts Discussed in Thread: LMK04000 , CDCM61001 , LMK03000 , CDCE62002 1.We require a 100MHz output clock frequency(LVPECL).Is it necessary to use PLL1?If not,can we power the PLL1 down and what are the parameters that are needed to be changed in order…
Part Number: LMK05318B Other Parts Discussed in Thread: LMK5C33216 , LMK5B33216 , LMK05028 , LMK5B12204 , LMK04033 , LMK04000 , LMK04001 , LMK04011 , LMK04010 , LMK04002 , LMK04031 , LMK04610 , CDCE813-Q1 Hi team:
I would like to confirm whether we have a low consumption…
Other Parts Discussed in Thread: LMK04000 , LMX2582 , LMK03318 Can you please recommend an appropriate clock jitter attenuation solution? Ideally with an eval kit available...
I have a pair of LVPECL clocks that range between 20MHz and 900MHz during normal…
Rotem,
Are you trying to verify if the digital outputs (data and clock) of the ADC are compatible with the Altera 2.5V bank input? If so, the answer is yes. Why are you mentioning the ADC input clock Vid? Do you plan on driving this with the Altera device…
Other Parts Discussed in Thread: LMK04000LMK04000 family's evaluation board schematic picture is not clear to see component How can I find clear picture of EVB schematic and second question is there are two ref. clock in(CLKin0/CLKin1) for lmk04033b…
Hi Edward,
This is dependent on the VCXO's Vpp. The LMK04000 family has a spec of minimum slew rate of 0.15 V/ns between 20% and 80%. What is the VCXO swing ?
Gabe
