Part Number: LMK04616 Other Parts Discussed in Thread: USB2ANY Hi,
Is it possible to configure an LMK04616 device implemented on a custom board (not an EVM) through USB2ANY dongle and TICS Pro software ?
Thanks in advance for your help.
Part Number: LMK04616 Hi Team, I would like to get some assistance regarding our customer inquiry with SYSREF timing of LMK04616 since it is not available in the datasheet or any application notes: Here's the content of the customer's questions:
…
Part Number: LMK04616 Greetings,
I want to confirm some info can't be found in datasheet.
What is the propagation delay between OSCin to Clkout(x). The device uses PLL2 (only) with zero delay mode.
Thank u.
Regards,
Part Number: LMK04616 Hi,
I am considering using two LMK04616 to distribute DCLK and SYSREF in an alternate manner in order to avoid as much trace crossing as possible. The SNAU22 document of multi-device synchronization does not address this configuration…
Part Number: LMK04616 Hello,
I want to use the LMK04616 in single PLL2 mode as described in data sheet Figure 52, with CLKin0 = 100 MHz and CLKoutX 1GHz:n (with n = 1, 2, 4, 8)
With my current initialization I do not have PLL2 locked. (PLL2 VCO is ~7…
Part Number: LMK04616EVM Other Parts Discussed in Thread: LMK04616 , CDCLVP1216EVM Hi
Please look at the attached diagram/snapshot I have attached, I want to connect LMK04616 board’s output clock as a source to CDCLVP1216EVM. But LMK04616 datasheet said…
Part Number: LMK04616 how to set LMK04616 to zero delay mode? where I can get more description about zero mode? pls provide reg setting base on following reg(I need CH6 feedback to pfd of PLL2).
R0 0x000000 R1 0x000100 R2 0x000200 R3 0x000306 R4 0x000438 R5 0x0…
Part Number: LMK04616 I have the same issue. I also need to add a delay after I generate a RESETN pulse. We have connected the LMK04616 EVAL board to an VC707 eval board. The power of both boards is up for a long time so the power supplies should be stable…
Part Number: LMK04616LMK04616_LVDS.docx
In the LMK04616 datasheet is stated that the minimal input swing of the CLKInx must be 400mV. The LVDS standard is 350mV. How does that work with the LMK04616 part?
According the datasheet the LMK04616 must be…
Part Number: LMK04616 Other Parts Discussed in Thread: LMK04832 I can't understand the phase relationship between the ClkinX and the sysclk .
Can you please see the attached wave-forms:
Assume the asynchronous sync pulse inserted to the clock distributed…