Part Number: LMK04616 Hi all.
I would like to know the Charge Pump value of PLL1. I use TICS pro and set Propagation Final value of PLL1. Is the Unit of propagation final value mA? I don't know the charge pump value from setting value of propagation. Please…
Part Number: LMK04616 Does TI have a clock solution that provides multiple frequency-phase-synchronized differential clocks; it also supports closed loop feedback from the output to the input, eliminating the phase shift caused by the external clock transmission…
Part Number: LMK04616 Other Parts Discussed in Thread: LMK04610 Hi,
We shall be using LMK series devices in clock generation (PLL 2 only Mode) and distribution mode to generate the below mentioned clocks:
LMK04616 - 105MHz and 10.5 MHz
LMK04610 - 90MHz…
Part Number: LMK04616 Hi all I would like to know the PLL2_RDIV setting procedure. My customer selects divider mode and value is 2. And they try to set 2 the following two pattern. Case1. Increase setting value from 1 to 2. Case2. Decrease setting value from…
Part Number: LMK04616 Hi,
We are operating LMK04616 in single PLL(PLL2) mode. The reference clock input to LMK shall be from a low noise TCXO. Please provide the Phase noise at output clock
105MHz
The reference clock phase noise is as mentioned below…
Part Number: LMK04616 Other Parts Discussed in Thread: LMK04610 , LMK04826 , CDCE72010 , , CDCI6214 Does TI have a clock solution that provides multiple frequency-phase-synchronized differential clocks; it also supports closed loop feedback from the output…
Part Number: LMK04616 Other Parts Discussed in Thread: LMK04828 , ADS42JB69 Dear Sir,
I want to calculate the RMS jitter noise for LMK04616 Dual- PLL for my custom output frequency with Ref Clock soruce and VCXO.
In datasheet, phase noise is mentioned…
Part Number: LMK04616 Hi all. If we do the following, LMK04616 all outputs stop. I attached the TICSpro picture. -We press the Soft Reset button during normal operation, and the outputs of the device stop. -We set "Device start" after that, the all output…
Part Number: LMK04616
After a Sync pulse to align the CLKout signals, they will be aligned a short time after the sync pulse. Is the timing of the moment of alignment related in any way to either of the following?
1. REF signal into PLL2 block.
2. …
Part Number: LMK04616 Hi,
I understand the PLL2REFCLKDIV Register controls the PLL2 Reference Clock Divider value for digital system clock. Then, what is the digital system clock for?
Best Regards,
Toshiyuki