Part Number: LMK1D2108 Other Parts Discussed in Thread: LMK1D1208 I'm using the LMK1D1208 as LVDS buffer in my design. I'm measuring on the hardware and noticed that the 8 outputs coming from IN0 are giving the inverted logic level. When a logic '1' is…
Part Number: LMK1D1204 Other Parts Discussed in Thread: LMK1D1208 , Hello,
Can you help share the preferred input layout of discretes/terminations to the LMK1D1205 device? Thanks, Zack
Part Number: LMK1D1204 Other Parts Discussed in Thread: LMK1D1208
Hi team,
Do you have information on the via pattern of the LMK1D1204?
The LMK1D120x datasheet contains via pattern information for the LMK1D1208, but it seems that the LMK1D1204 does not…
Part Number: LMK1D1204 Other Parts Discussed in Thread: LMK1D1208 Hello Team,
may I ask you to provide the voltage levels in case the outputs are not terminated with 100 Ohm for the supply voltage of
Vdd VOUTP or VOUTN high level
3.3V ?
2.5V ?
1.…
Hi Charles,
Please refer to this past e2e post on resistor value suggestion for the LMK00306.
Alternatively, depending on your input requirements, you could use the LMK1D2104 or LMK1D1208 LVDS buffers. The LMK1Dx family does not require the DC path.
Regards…
Hi JF,
We do not have additional information available about peak-to-peak jitter for the CDCLVD1208. I recommend our newer part, LMK1D1208, instead for improved jitter performance:
Regards,
Jennifer
Part Number: LMK1D1212 Other Parts Discussed in Thread: LMK1D1208 Hello,
It is not clear from the Datasheet of LMK1D1212 how to connect the unused Input clock pins.
On the one hand it is written on page 14 of the datasheet :
Unused inputs can be left…
TI’s wide portfolio of RF PLLs & synthesizers features devices that are potential crosses for Analog Devices HMC103x, HMC7xx, HMC8xx PLL family products and other discontinued products such as ADF5610 and HMC987. With most of TI’s RF PLLs &…
Part Number: LMK1D1208P Other Parts Discussed in Thread: LMK1D1204 Problem 1: LMK1D1208P is used as the clock buffer. Three 100Ms from the same chip are used as the system clock of three FPGAs. Two of them are OK. One of them has a problem with the clock…