Part Number: SN74ALVCH16374 Hi
my customer use SN74ALVCH16374 at 1.8V system.
The DS page 5 about switch characteristics hasn't show 1.8V information.
is there any spec information about 1.8V?
Hi Akash, I think the connection of GPMC_AD0 to A1 and DQ0 is correct. Sorry if I confused you. I checked the 74ALVT16373 datasheet again, and confirmed that the latch enable inputs are active HIGH, latching the inputs on the falling edge (and passing…
Hi Bhaskar,
Bhaskar Reddy said: We are planning to use latches (eg SN74ALVCH16374 ) to support 256K Bytes of SRAM (as given in example interface with NOR flash here Can anyone please confirm, this is feasible or not.
Yes, this is feasible but please…
Hello Biser,
Thank you for your reply.
We checked the hardware layout of flip-flop(SN74ALVCH16374), which was reversed in all D and Q pins.
Current, the GPMC is able to access the SRAM in bootloader(MLO) layer only.
The GPMC ( config ) registers…
I have tried adding pullups and even pull down without any sucess.
The possible reason being SN74ALVCH16374 , The 16 bit bidirectional edge Triggered D- Flipflop has a input BUS-HOLD function, that holds on the previous data on the BUS , which might…
Other Parts Discussed in Thread: SN74ALVCH16374 , AM3352 Hi,
I would like to use a small SRAM and a Nor Flash for the GPMC Bus. Can this be done NOT using a SN74ALVCH16374 (as it's done in the ICS board).
The ZCE package have the GPMC_Axx pins spread…
Fmax will not be specd on buffers. It is only spec on devices with clocks. The easiest way to find Fmax is to look at a clocked part in that family.
I looked at the SN74ALVCH16374 . It is best to choose a part with the same amount of outputs. or at…
There is an example of this type of implementation on the following wiki article . Although the article is centered around a different device, the concept is the same.
Look for the illustration entitled " 16-bit NOR with external latch".
Using a SN74ALVCH16374…
Philippe,
I think you're right! I've seen similar things done before, but this one is just a little different. I think a workable solution would be to use SN74ALVCH16374 and tie nadv_ale to the CLK pin.
I'm separately contacting the author of that…
