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LMV761: Shutdown pin input characteristics

Joseph Lee
Prodigy 20 points
Part Number: LMV761
Other Parts Discussed in Thread: TLV4021, LM393LV, TLV7011, TLV9022, TLV7021, TLV4031, TLV4051, TLV4041

Hi, does someone know what the input characteristics of the shutdown pin of the LMV761 are? Specifically, what are the logic thresholds (presumably related to Vcc) and what is the input impedance? I understand that the shutdown pin should not be left floating, but for my application I do not want to tie it directly to Vcc or GND and instead would like to have it tied to GND through a pulldown resistor and then driven high by an MCU when desired. The datasheet does not seem to specify the necessary data in order to select an appropriate pullup/pulldown resistance value.

Thanks,

Joseph

  • +1
    TI__Guru 51446 points

    Hello Joseph,

    The Applications section describes the shutdown pin, section 7.4.1.

    It states the shutdown levels are proportional to supply voltage, which tells me that it is probably an "inverter" type digital input with a N and P channel MOSFET with the gates tied together.

    The admonition to not "three state" or float the input is also a clue (as both MOS could be on at the same time if the input voltage is floated within the "middle" of the range). That could lead to increased supply current. This also rules out an internal weak pull-up or pull-down.

    The SD input is CMOS, and would have pA currents similar to the inputs. The resistor value could theoretically be up into the Megohms - depending on how much current you can burn.

    The logic threshold levels would be a Vgs from the rail, or about 800mV to 1V away from the corresponding rail.

    So I would try to get the SD input voltages as close to the rails as possible. In other words, I would not put 3.3V on the SD pin with a 5V supply.

    What is the supply voltage for the comparator and MCU?  How much power can you "waste" during shutdown?

    The comparator is shutdown then the SD pin is grounded.

    You could pull-up to V+ and use an open drain output to pull low, if the MCU has 5V compatible I/O pins (or an external MOSFET).

    If you need to save power during SD, then you would need a pull-down resistor and a P-channel MOSFET on the high-side to pull-up to V+.

  • 0 in reply to Paul Grohe
    Prodigy 20 points

    Paul,

    Thanks for you quick response! The comparator and MCU are both powered from 3.3V and I am somewhat flexible about wasted power during shutdown since the plan is to have the comparator enabled continuously after the MCU boots.

    Essentially the application is to provide hardware overvoltage protection for an MCU controlled PFC boost converter so that during firmware development the circuit is protected in case the firmware OVP fails to operate properly. The comparator inverting input is fed from a 1.65V reference voltage derived from the 3.3V rail. The non-inverting input is fed from a voltage divider from the PFC boost output voltage (which comes up to the rectified mains voltage well before 3.3V comes up). I have the comparator configured with very high hysteresis so that the comparator latches high and the board must be powered off to reset. The output of the comparator drives downstream circuitry that enables PWM signals to the boost converter's gates when the output of the comparator is LOW and disables PWM output when the comparator output is high impedance or HIGH. The reason I want the comparator to default to disabled rather than default to enabled is so that the comparator stays disabled at power up (output high impedance) until the reference voltage is high enough to guarantee that the output will not latch high falsely

    Perhaps there are better ways to prevent the comparator from latching high during power up? - essentially what I need is for the comparator output to stay high impedance until Vcc (the 3.3V rail) reaches a minimum of 2.9V. I would assume the comparator has some sort of UVLO threshold, but I suspect that threshold is much lower than 2.9V

  • 0 in reply to Joseph Lee
    TI__Guru 51446 points

    Hello Joseph,

    If both the comparator and CPU are at 3.3V, then you can drive the input directly. Maybe a 100k pull-down to make sure any turn-on transients don't pull it high.

    The older comparators do not have a UVLO (we call POR), they just start up when they hit their minimum operating voltage and the internal bias circuitry stabilizes. It's not controlled so there is no guarantee about start-up behavior on any of the previous devices.

    We do have newer comparators that have a Power-On Reset (POR) feature, that keep the output in a known state until the minimum supply voltage is reached and after a slight time delay (20-30us).

    See the TLV7011, TLV9022, LM393LV, and TLV4021 series:

    For the TLV7011 family (PP out), the POR circuit will hold the output low (at VEE).

    For the TLV7021 family (OD Out), the POR circuit will keep the output high impedance (logical high).

    For the TLV9022 and LM393LV family, the POR circuit will keep the output high impedance (HI-Z).

    For the TLV4021 and TLV4031, the POR circuit will force the output to High-Z,

    For the TLV4041 and TLV4051, the POR circuit will hold the output low at (V-).

    Remember - that's from the comparators minimum V+ supply..not your monitored voltage. About 1.5 to 1.6V for the above devices.