• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 48 subscribers
  • Views 168 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV4041: TLV4041

Genrikh Kleynerman
Prodigy 70 points
Part Number: TLV4041

Hi,

I am designing in the TLV4041R5DBVR push-pull part (I would prefer Open Drain, but unfortunately, there is no Open Drain part in a package larger than tiny DSBGA). I need to connect the output of this comparator to the LVCMOS18 input of FPGA (both the comparator and FPGA Bank use 1.8V supply). The only info on VOL/VOH for this comparator in the data sheet is this:

I have no control over Isource (what is it by the way?), and my Vs=1.8V. My feeling is the FPGA pin will switch OK, as FPGA's VILmax=0.63V and VIHmin=1.17V, but how do I come up with correct numbers for VOL/VOH here? the FPGA pin leakage current is <|15|uA.

  • +1
    TI__Mastermind 24160 points

    Genrikh

    Thanks for posting your question and sorry for the confusion.  From the leakage current of the FPGA pin (15uA), we can conclude that the input impedance is quite high (from typical performance curves the voltage drop from V- and V+ will be less than 10mV).

    So we do not expect any problem meeting the logic high and low levels of the FPGA with the output of the comparator if powered with a VS = 1.8V.  Open drain is generally required if you need to level shift the output voltage or if outputs need to be combined into a single line.  It does not sound like either of those are needed for your application, so I would actually be suggesting you use a comparator with a push pull output stage.

    Chuck

  • 0 in reply to Chuck Sins
    Prodigy 70 points

    Chuck,

    Got it. 

    Thank you!