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OPA2197: OPA2197

Part Number: OPA2197

Dear Ti Expert,

I am using OPA2197 (Vs=5V -Single supply )  for my application and calculating worst case offset voltage due to PSRR

below is the snapshot of the OPA2197 and highlighted parameter I am using for calculating offset voltage due to PSRR

Offset Voltage due to PSRR=( 8V-5V)*2=6 uV    where 8V= maximum supply for the given PSRR specification 

                                                                                       5V= Application Supply Voltage for OPA2197

Is my approach correct?

2. My second question is while calculating offset voltage due to CMRR which CMRR specification should I consider ?

below is the snapshot of OPA2197 datasheet.

  • I forgot to mention above question for OPA2197-Q1 part no

  • Hi Biswajit,

    your calculation of PSRR is correct. But keep in mind that because only typicals are given for the PSRR, the true PSRR can vary a bit. See also figure 16.

    Referring to your second question, this depends on where your common mode input voltage will sit in your application. Best you read section 7.3.6 of datasheet.

    Kai

  • Thanks Kai for your response.

    I have one follow up question if I take (4.5 -5)*2 =-1uV where 4.5 voltage min specification supply voltage 

                                                                                           5V=Application supply voltage for the Opamp

    so would it give min Offset voltage due to PSRR? I know that PSRR specification is the typical one so it will not be absolute min value but rough estimation.

    Please let me know your thoughts

  • Hi Biswajit,

    the input offset voltage of OPA2197 changes by about 1µV when the supply voltage changes between 4.5V and 5V.

    Kai

  • Hi Biswajit,

    Here is how I interpret the OPA2197-Q1's specification. 

    Vs = 4.5Vdc to 8Vdc refers to low voltage specification (dual and single supply operation) in OPA2197-Q1 part. If the Vs supply voltage is between 4.5Vdc to 8Vdc, then typical PSRR is expected to be at approx. ±2uV/V. 

    If a supply voltage is 5Vdc and ripple noise is 1Vpk from 4Vdc to 6Vdc (say near DC or low frequency), then Vos will be affected by ±2uV from PSRR. Of course, the 5Vdc power supply with the such ripple is not very good regulator. Enclosed plots are captured from OPA2197-Q1's datasheet.

    Also, PSRR is a function of noise frequency. Per the example above, if the same ripple voltage has ±1Vpk voltage ripple on 5Vdc at 1kHz, the typical PSRR will be approx. 80dB rejection or 1/10^(80dB/20) = 100uV/V. In this scenario, Vos may be affected up to ±100uV/V due to the noises from the power rail. 

    https://training.ti.com/ldo-basics-power-supply-rejection-ratio-psrr

    2. My second question is while calculating offset voltage due to CMRR which CMRR specification should I consider ?

    If you know the operating Vcm range, you need to pick the worst case or the minimum CMRR specification, and try to avoid the transition region in Vcm voltage in this part. Say CMRR = 84dB is the worst case over temperature, then it may contribute up to 1/10^(84dB/20) = 63 uV /V to Vos under the worst case operating temperature. But under the nominal operating conditions, OPA2197-Q1's CMRR is specified 140dB or 0.1uV/V, which is excellent, see Figure 16 of the datasheet. 

    If you have additional questions, please let us know. 

    Best,

    Raymond

  • Hi Biswajit,

    I am going to close this inquiry. If you have additional questions, you may still reopen the thread or create a new one via E2E forum. 

    Best,

    Raymond