LMC7211-N: Placing two LMC7211-N in parallel to increased output drive

Marvin

Thanks for your post and excellent question.

In general it is not recommended since the two devices can have slightly different delays/offsets/etc and then the outputs could be fighting each other.  However, this doesn't necessarily mean the idea is bad.  My preference would be to use a dual device if possible where the channel to channel variation is less (same substrate = better matching).  If that is not possible, then I would suggest limiting the effect of potential output conflicts by adding a 10 ohm resistor on the output of one of the comparators.  You will still achieve the benefit of having the devices in parallel without risking damaging the output stages.

Chuck

Hi Marvin,

paralleling of outputs of OPAmps, comparators and digital buffers is always critical and requires careful development efforts. It's true that by the help of equalization resistors being inserted into the paralleled outputs the danger of damage can be avoided. But if the outputs are not switching absolutely synchronously, a very short lasting "shot through" current can flow from one output into the other and by this generate a very high current spike running through the internal supply lines of chip. Because the current spike is very short lasting and runs across the non-negligible inductance of bond wires this can end in a very high internal ground bounce massively shifting the ground potential of chip. This would even happen with an excellent supply voltage decoupling because the bond wire inductance is sitting internally of chip, outside the sphere of action of external decoupling cap.

The ground bounce is problematic because every potential on the chip is shifted by it. This can destabilize the circuit and cause oscillation. In any case it should be verified by measurement that such a "shot through" current is not occuring. Because the speed of comparators varies with temperature, this measurement should be carried out at varying ambient temperatures. And it should be considered that the speed of a comparator can show huge manufacturing tolerances from chip to chip. Because of that Chuck's suggestion to use a dual device cannot be emphasized enough.

By the way, for the same reason a comparator should never directly discharge a heavy capacitive load at the output without any current limiting. This can also result in a massive ground bounce. In such cases always a current limitng resistor should be added. I have seen many unstable and wildly oscillating comparator circuits which could be simply cured by inserting a small current limiting resistor between the output of comparator and the capacitive load.

What does all this mean for your application?

1. As recommended by Chuck, you should use a dual device.

2. You need equalisation resistors in the paralleled outputs.

3. Because of driving a capacitive load, you definitely need a current limiting resistor. The equalization resistors can play the role of this current limting resistor at the same time.

4. Driving a capacitive load can help to prevent the nasty "shot through" current, provided the time constant of equalization resistors (current limiting resistor) and capacitive load is much bigger than the output toggle time of comparator. Then, the capacitive load keeps the voltage across this capacitance automatically constant during the toggling period and only one output at a time can source or sink current. (It's assumed that the capacitive load is either fully charged or fully discharged before the toggling.)

5. If you still suffer from too high ground bounce, even with a current limiting resistor, it might be a good idea to separate the comparator section and load buffer section and use two different devices, a comparator and an additional buffer for the capacitive load.

Kai

The easiest solution would be to add a digital buffer after the comparator; something like the SN74LVC1G34 or UCC27517, depending on what voltage and drive strength you need.