AMC1350: questions to understand AMC1350

Hello Takahashi-san,

1. No concerns. They will lose some SNR performance from what is specified in the AMC1350, similar to AMC1351. 

2. I cannot disclose construction details of our devices on the public forum. I will contact you offline.  

3. The single-ended input signal is converted to a digital bitstream by the modulator, sent across the isolation barrier, then reconstructed on the low side through a digital filter. Please see figure 7.2 for simplified block diagram and this article: https://www.electronicdesign.com/power-management/whitepaper/21130089/texas-instruments-introduction-to-isolated-amplifiers-and-modulators for additional information. 

4. A CMTI failure corrupts the bits passing over the isolation barrier and appears as a small offset lasting ~3uS for a single event. More severe events may increase the magnitude or duration of the offset on the output. 

5. Yes. This can be seen in 7.3 Recommended Operating Conditions of the TLV6001 datasheet. 

6. This will depend on your signal amplitude and bandwidth requirements of the ADC and end equipment. Please see design steps 5-9 of this document: https://www.ti.com/lit/an/sbaa347/sbaa347.pdf and this tech note for further details: https://www.ti.com/lit/an/sbaa229a/sbaa229a.pdf

Hi Takahashi-san,

Apologies I missed your follow-up question. The magnitude of the offset is dependent on the severity common-mode transient and how many bits are corrupted as a result of the transient. For example, a single bit failure will result in an offset of approximately 60mV whereas a 3x bit failure will result in an offset of approximately 170mV.