ALM2403-Q1: ALM2403-Q1

Hello Jacob,

We had already had an discussion previously before purchasing this OPAMP. Below is the link for the same:

ALM2402-Q1: ALM2402-Q1 - Amplifiers forum - Amplifiers - TI E2E support forums

I wanted to use ALM2403-Q1 for current amplification for analog signals from my source(NI FPGA card) .

I did connection according to above comments .

Do you have thermal pad soldered down? You may need this thermal pad to connect to something to dissipate heat during operation. 

- NO I didnt. Is this mandate as I am amplifying analog signals(0-10v) from 4ma to 70mA  .

If it is mandate , how can i do this ? I had mounted this IC on a 14pin IC adapter.

Hello Jacob,

1. Okay I will keep  pin 1(IN-1) to pin 13(OUT1) shorted by default in the IC and then take amplified Analog out from pin 13 . Also pin1(IN1-) should be connected with GND  of  analog source correct? in my case NI FPGA GND.

2. Pin 3: OTF/SHDN pin

I have -3.3v , -5v available in my SMPS . Can I source -5v to Pin 3? 

3. yes I will be using  CH2 of amplifier too .

Can you summarize me any particular point in connections to be taken care when using both CH's of this Amplifier.   

Also in case if I am only using CH1 , then I should connect GND to IN2+ {pin 4} . correct?

Hello Jacob,

OTF/SHDN pin

Above is the voltage range for OTF/SHDN pin.

V- is  -12V  so range is [-12-0.2] to [-12 + 5.7] => -12.2V to -6.3V.

So how about providing -12V itself which is in above range

okay.

So voltage in this range  [-10.8V to -6.3V]  should be applied at OTF/SHDN pin.

So using +12V and -12V, which is 24V, A voltage divider ckt with R1=10Kohm ,R2=2.2Kohm will give me Vout across R2  = -7.68V .

This is good? pls confirm 

Thanks

I will test and let you know the feedback

Perfect, this should work well after the change.

Thanks!

Jacob

ALM2403-Q1_CKT_Board Design.pdf

Request you to Please review this design ! 

I am getting continuity across V+ and V- in this design which is not expected. Please help analyze what is wrong here. 

Pin 1 connected to pin 13

Pin 2 connected to your input module

Pin3 connected to a voltage -7.68V . 1/4 watt resistors used.

Pin 6 and  Pin 14 connected to V- (-12V)

Pin 10, pin 11, pin 12 connected to V+ (12V)

Hi Vishnu,

This is a sound design, good connections at every pin. 

When you say continuity across V+ to V- you mean you are measuring with a DMM and finding low resistance path between terminals?

What is the reading at OUT1 when you connect to the pin 2 to GND? 

Thanks,

Jacob

yes when i do continuity check using DMM across V+ AND V- , I am getting beep sound(they are shorted). Also I could see spark coming and i immediately disconnected power.

Ya. Asper design also there should not be a short between V+ and V-  I could see and not even when tested across pin 6 and 10 of the IC alone (without other ckt).

Confused and debugging!!

1/4 watt resistors are good? 

Yes, thanks for your patience as we work through this problem. 

I will have time to solder the part to an adapter board like you are using in ~3 hours from now. I can send you over my results when I hook the part up to my test equipment. 

How is the circuit being ground referenced? Do you have anything which connects to the DGND of the input module? 

Best,

Jacob

okay. Thanks for your support on this.

How is the circuit being ground referenced? Do you have anything which connects to the DGND of the input module? 

- NO. NI FPGA DGND is not connected to any pin of amplifier or CKT

Hi Vishnu, 

Thanks, this is good to know. 

I will report my test results in the next couple of hours. 

Best,

Jacob

Hello Jacob,

I did make the circuit freshly . No I dont have short between V+ and V- .

Observations//

1. 24V measured across V+,V-  // Expected.

2. 11.5V measured across IN1+ and common GND(GND of PS) . // Not expected

3. 11.5V measured across Out1 and common GND(GND of PS) . // Not expected

After I connect my source Analog out signal (0-5v) at IN1+ also same 11.5v was measured at IN1+ and OUT1 aswell .

Please help debug what might be wrong here!!

Hi Vishnu,

Good to hear that the short is fixed.

It is strange to hear that the IN+ is set to 11.5V.

Could you try connecting this pin to the PSU common GND?

What is SHDN voltage measured under the following two conditions:

voltage between SHDN and V-

voltage between SHDN and PSU common

Best,

Jacob

voltage between SHDN and V- // 22.2V

voltage between SHDN and PSU common // 10.9V

Could you try connecting this pin to the PSU common GND? //  Which pin I should try connecting to PSU Common GND?

Connect IN+1 to GND common. 

Thanks,

Jacob

IN1+ is where I will connect Source AO signal , so I should not connect both  

Hi Vishnu, correct, we cannot connect both at the same time. 

I am concerned why the voltage between SHDN and V- is 22.2V. This would mean we are at 22.2V-12V = 10.2V relative to GND or about 10.9V as you measure.

We should be at V- +5.7V at most. Weren't we targeting to be at something like -7.68V relative to GND?

Thanks,

Jacob

So I connected PSU GND to IN+1 .

voltage between SHDN and V- // 22.2V

voltage between SHDN and PSU common // 8.2V

Weren't we targeting to be at something like -7.68V relative to GND?

yes

Hi Vishnu, 

Did we get the resistor divider backwards?

Technically this OTF/SHDN voltage is currently damaging the device. In fact, it may be likely that this voltage has damaged the device to a point where it will not operate correctly now. I had success with the 10k and 2.21kohm resistor for setting the OTF/SHDN pin voltage. 

Can we swap some of the resistive components around to fix this voltage setting?

Thanks,

Jacob

Before applying 12V+,12V- Voltage to CKT, I verified:

 1. Resistor across pin3 and V- as 2.2kohm and across pin3 and V+ as 10kohm . 

2. No shorting between :

V+,V- 

IN1+,IN2+

Out1,Out2

3. Continuity check also verified to confirm the implementation asper the ckt board design .

After applying the power ,12V+,12V- Voltage to CKT, I verified:

1. There is shorting between V+,V-

2. Pin 14 is shorted to pin 10,11,12 and V+

*NOTE:  I removed IC from Ckt board and then checked  if these pins are still shorted within the IC and yes it was shorted .

This means after applying power to  IC, IC  had damaged which had resulted in this shorting within IC .

I experimented with 2 of my IC's and both are damaged now . The IC is very sensitive or not sure why this is happening .

TI OPA547T //

How about this Amplifier? Can this be used for same application? 

Would this be better as "ALM2403-Q1" IC is very much sensitive I feel

Hi Jacob,

I am not sure why this would be the case. ALM2403-Q1 is actually pretty strong when it comes to overstress tolerance and ESD.

-> Not sure as the ckt design is verified from your side and we connected it same way. Else can you again revisit the CKT diagram shared or provide your own ckt diagram from scratch to freshly approach this ?

EVAL Boards are not preferred due to higher price .  

Considering OPA593, What are the things to be taken care in electrical connection to use it for our application? 

The Design you had provided and the previous design are attached here.

In old design V+ =12v , V- = -12V and voltage across 2.2kohm with reference to V- (-12v) was passed to pin 3 .

In the new design you have provided, Voltage across 10kohm with reference to 0V  is passed to pin3.

Above is one key differance I observed.

The GND reference you mentioned in new design, at IN2+ and at 10Kohm resistance  should be Source AO channel GND ?

Hello Jacob,

I did connections asper your new design . I didn't get any pin short here which is good but the voltage out is not as expected.

Below I will provide the voltage observed at Out1+ with respect to Voltage provided at IN1+ ;

IN1+   Out1+

1v -     0.110
2v-     1.10
3v-     2.10
4v-     3.09
5v-     4.09

0.0v-   -0.835
0.1v-   -0.76
0.2v-   -0.68
0.5v-   -0.38
0.8v-   -0.081
0.9v-   0.018

Out1+ voltage is measured across Out1(pin13) and Common GND.

Please analyze and provide solutions

Hey Vishnu, 

Thanks for taking this data, it is interesting to see.

We are running out of options here for debug, but i am determined to get this circuit working. I built the exact circuit we had originally with no issue. My new revision of the circuit is very similar, so I would expect this to work as well. 

I find it interesting that the OUT+ is off by .9V consistently. This is very strange. I have seen cases like this where the op amp self powers through the ESD diode path https://e2e.ti.com/blogs_/archives/b/precisionhub/posts/the-self-powering-device. It might be worthwhile to probe pins 10-12 relative to GND. 

Can you take a picture of your board? I want to make sure everything is correct.

Are you able to measure the current flowing into the supply rails of the device? This can tell us what the device is trying to do. 

Thanks,

Jacob

Voltage across pin3 and GND is  -9.45V

CKT board snap attached.

The power source is an SMPS , and so cant measure the current draw by the ckt .

Pin 10,11,12 are internally shorted within IC , hence only pin12 was connected to V+

Hi Vishnu,

I believe this is the case, but it appears that the output stage is not using any drive voltage. 

For fun, could you connect these pins to 12V?

Thanks,

Jacob

Vishnu, 

If this does not solve the problem, then the 12V rail may not be functioning, or the device may not be making connection with 12V rail. 

Thanks,

Jacob

Hello Jacob,

I did connect pin 10,11,12 to V+ and the circuit is functional now .

The output is inline with the IN1+ voltage provided. 

But there in an increasing deviation in the voltage measured at OUT1 wrt IN1+ as we increase voltage say (IN1+ = 0.1v TO 5V) .

I have captured the observation in word file attached.

#NOTE:

In the screenshots attached please note : I have integrated Current amplification module for only FLOCK signal and its associated SW variable read is  "Appl_Flock_Asil_buffer.Volt". Refer .jpg file attached. Curr_amplifier test.docx

Is there anything we can do for reducing this deviation ?

Hey Vishnu, 

Some error will come from the breadboard, this is non-ideal layout for the device. 

What is reading this output voltage?

It looks like .8V setting is getting readback of .760V

It looks like 4.997V setting is getting readback at 4.835V, correct?

It may be necessary to put a low pass filter before your ADC is you are trying to readback accurate voltage. 

Have you confirmed that the actual output voltage is accurate relative to what your software is reporting?

Thanks,

Jacob

Hey Vishnu, 

Happy to help!

Great to hear that this design is suitable. Please reach out if any other questions come up.

Thanks,

Jacob