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LM2907 simulation model

Toshiyuki
Mastermind 7075 points
Other Parts Discussed in Thread: TINA-TI

Hi,

Do you have the simulation model of LM2907?

HSpice,PSpice,TINA-TI,,,

Best Regards,

Kato

  • 0
    TI__Guru 55056 points

    Hello Kato,

    There is no official SPICE model for the LM2907/LM2917, but there are some on the Web built by third partys.

    Google "LM2907 SPICE model" and you will find a few of these.

     https://forum.allaboutcircuits.com/showthread.php?t=38423

     http://forum.allaboutcircuits.com/showthread.php?t=38554

     TI does not support these models, but they are better than nothing.

    Note that there are differences between the LM2907 and LM2917, particularly with the power supply and input stage thresholds.

    Regards,

  • 0 in reply to Paul Grohe
    Prodigy 40 points
    For anyone else who lands up here looking for LM29x7 family spice models: there are now a family of spice models for the LM2907-8, LM2917-8, LM2907-14 and LM2917-14 devices available from EasyEDA.com/editor.

    There's a demonstration of the LM2907-8 here:

    easyeda.com/file_view_LM2907-driven-by-Hall-sensor_bL3WewOI0.htm

    and for simplicity I have pasted the models in below (please check carefully for any line-wrap induced errors!).

    They are written for ngspice but should run unaltered in LTspice and Pspice.

    Enjoy.

    :)

    ***************************************************************************
    * LM2907 8 pin model
    *
    * Spice subckt of LM2907 in 8 pin package.
    * Developed for EasyEDA from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf
    * by signality.co.uk
    *
    * Last edited 150412
    **
    .SUBCKT LM2907_8EE TACHINP PUMPCAP CHARGECAP EMITTER COLLECTOR VCC OPINN GND
    *RNC1 NC1 0 1T ; comment out for LM29x7_8
    *RNC1 NC2 0 1T ; comment out for LM29x7_8
    *RNC1 NC3 0 1T ; comment out for LM29x7_8
    *RNC1 NC4 0 1T ; comment out for LM29x7_8
    Vlink1 TACHINN GND 0 ; comment out for LM29x7_14
    Vlink2 CHARGECAP OPINP 0 ; comment out for LM29x7_14
    .param IUP = 200u IDN = IUP
    + hith = 15m ; V. Upper threshold.
    + loth = -15m ; V. Lower threshold.
    + Vabsmax = 28 ; V. Absolute maximum supply voltage
    * Applies to VCC for LM2907 only and total across output
    * transistor or from COLLECTOR to GND for all devices.
    + iq = 3.8m-265u ; A. Quiescent current (less total of current sources).
    * Excldes current through zener on LM2917 devices.
    **
    * Quiescent current, supply zener and reverse voltage clamp
    *
    Diq_reverse_n_oversupply 0 VCC Drails
    **
    * Input resistances, rail clamps and bias currents
    RTACHINP TACHINP 0 1G
    RTACHINN TACHINN 0 1G
    DTACHINPVCCclamp TACHINP VCC Dclamp
    *DTACHINPGNDclamp 0 TACHINP Dclamp ; comment out for LM29x7_8
    RSER TACHINP TACHINPX 10k
    DTACHINPXGNDclamp1 TACHINPX 0 Dclamp ; comment out for LM29x7_14
    DTACHINPXGNDclamp2 0 TACHINPX Dclamp2 ; comment out for LM29x7_14
    *DTACHINNVCCclamp TACHINN VCC Dclamp ; comment out for LM29x7_8
    *DTACHINNGNDclamp 0 TACHINN Dclamp ; comment out for LM29x7_8
    BITACHINP VCC TACHINP I=LIMIT(200n*V(VCC,TACHINP), 0, 100n)
    *BITACHINN VCC TACHINN I=LIMIT(200n*V(VCC,TACHINN), 0, 100n) ; comment out for LM29x7_8
    **
    * Input stage with hysteresis
    Binschmitt 0 outschmitt1 I=0.5*(tanh((V(TACHINPX,TACHINN)-loth+(V(outschmitt1)-1)*(hith-loth))*1k)+1) ; non-inverting
    Rinschmitt 0 outschmitt1 1
    Cinschmitt 0 outschmitt1 100n
    *
    BV1 offsetschmitt1 0 V=V(vcc)/2*V(outschmitt1)+V(vcc)/4
    **
    * Charge pump stage
    B1 0 N001 I=0.5*(IUP+IDN)*(tanh(V(offsetschmitt1,pumpcap)*1k)+(IDN-IUP))
    Lconvfix1 N001 N002 1n ; unclear as to why but significantly improves convergence
    Rconvfix1 N001 N002 1G ; optional damping for Lconvfix1
    Vimon1 N002 PUMPCAP 0
    R1 PUMPCAP 0 1G
    C1 PUMPCAP 0 1f
    **
    * Pumpcap output rail clamps
    DPCAPVCCclamp PUMPCAP VCC Dclamp
    DPCAPGNDclamp 0 PUMPCAP Dclamp
    **
    * Charge mirror stage
    B2 0 N003 I=ABS(I(Vimon1)) ; I=uramp(I(Vimon1))+uramp(-I(Vimon1)) ; alternative ABS function
    R2 N003 0 1G
    C2 N003 0 1p
    **
    * Charge mirror output stage
    D1 VCC N004 Dclamp
    D2 N004 N005 Dclamp
    BCHGOP N005 0 I=LIMIT(400u*V(N005), 0, 200u)
    QCHGOP CHARGECAP N005 N003 PN
    R3 CHARGECAP 0 10Meg
    C3 CHARGECAP 0 1f
    **
    * Chargecap output rail clamps
    DCCAPVCCclamp CHARGECAP VCC Dclamp
    DCCAPGNDclamp 0 CHARGECAP Dclamp
    **
    * Opamp input resistances and rail clamps
    ROPINP OPINP 0 1G
    ROPINN OPINN 0 1G
    *DOPINPVCCclamp OPINP VCC Dclamp ; comment out for LM29x7_8
    *DOPINPGNDclamp 0 OPINP Dclamp ; comment out for LM29x7_8
    DOPINNVCCclamp OPINN VCC Dclamp
    DOPINNGNDclamp 0 OPINN Dclamp
    **
    * Opamp/comparator and floating output transistor stage
    * (modelled directly from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf)
    Q35 0 OPINN Q36B PN
    BIQ35E VCC Q36B I=LIMIT(6u*V(VCC,Q36B), 0, 3u)
    Q38 0 OPINP Q37B PN
    BIQ38E VCC Q37B I=LIMIT(6u*V(VCC,Q37B), 0, 3u)
    Q36 QD1C Q36B TAIL PN
    Q37 COMP Q37B TAIL PN
    BITAIL VCC TAIL I=LIMIT(12u*V(VCC,TAIL), 0, 6u)
    QD1 QD1C QD1C 0 NP
    Q39 COMP QD1C 0 NP
    Q40 0 COMP Q41B PN
    BIQ40E VCC Q41B I=LIMIT(6u*V(VCC,Q41B), 0, 3u)
    Q41 VCC Q41B Q41E NP
    Q42 Q41B Q41E Q43C NP
    Q43 Q43C Q41E 0 NP
    RQ41E Q41E 0 100k
    BIQ43C VCC Q43C I=LIMIT(100u*V(VCC,Q43C), 0, 50u)
    Q44 VCC Q43C Q44E NP
    CCOMP Q43C COMP 10p
    RQ45B Q44E Q45B 5k
    RQ45E Q44E EMITTER 15k
    Q45 COLLECTOR Q45B EMITTER NP
    **
    * Collector supply overvoltage and reverse voltage clamp
    * and emitter reverse voltage clamp
    DCOLLECTOR COLLECTOR 0 Drails
    DEMITTER 0 EMITTER Dclamp
    *
    .model PN PNP(BF=100)
    .model NP NPN(BF=100)
    *
    **
    * Models
    .model Dclamp D Is=1e-12 N=1 Rs=1
    .model Dclamp2 D Is=1e-12 N=0.1 Rs=1
    *.model Drails D Is={iq} N=2 BV={7.56} IBV={iq*10} Rs=10.5 ; comment out for LM2907
    .model Drails D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1 ; comment out for LM2917
    .model Dcollector D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1
    *
    .ENDS LM2907_8EE
    ***************************************************************************


    ***************************************************************************
    * LM2917 8 pin model
    *
    * Spice subckt of LM2917 in 8 pin package.
    * Developed for EasyEDA from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf
    * by signality.co.uk
    *
    * Last edited 150412
    **
    .SUBCKT LM2917_8EE TACHINP PUMPCAP CHARGECAP EMITTER COLLECTOR VCC OPINN GND
    *RNC1 NC1 0 1T ; comment out for LM29x7_8
    *RNC1 NC2 0 1T ; comment out for LM29x7_8
    *RNC1 NC3 0 1T ; comment out for LM29x7_8
    *RNC1 NC4 0 1T ; comment out for LM29x7_8
    Vlink1 TACHINN GND 0 ; comment out for LM29x7_14
    Vlink2 CHARGECAP OPINP 0 ; comment out for LM29x7_14
    .param IUP = 200u IDN = IUP
    + hith = 15m ; V. Upper threshold.
    + loth = -15m ; V. Lower threshold.
    + Vabsmax = 28 ; V. Absolute maximum supply voltage
    * Applies to VCC for LM2907 only and total across output
    * transistor or from COLLECTOR to GND for all devices.
    + iq = 3.8m-265u ; A. Quiescent current (less total of current sources).
    * Excldes current through zener on LM2917 devices.
    **
    * Quiescent current, supply zener and reverse voltage clamp
    *
    Diq_reverse_n_oversupply 0 VCC Drails
    **
    * Input resistances, rail clamps and bias currents
    RTACHINP TACHINP 0 1G
    RTACHINN TACHINN 0 1G
    DTACHINPVCCclamp TACHINP VCC Dclamp
    *DTACHINPGNDclamp 0 TACHINP Dclamp ; comment out for LM29x7_8
    RSER TACHINP TACHINPX 10k
    DTACHINPXGNDclamp1 TACHINPX 0 Dclamp ; comment out for LM29x7_14
    DTACHINPXGNDclamp2 0 TACHINPX Dclamp2 ; comment out for LM29x7_14
    *DTACHINNVCCclamp TACHINN VCC Dclamp ; comment out for LM29x7_8
    *DTACHINNGNDclamp 0 TACHINN Dclamp ; comment out for LM29x7_8
    BITACHINP VCC TACHINP I=LIMIT(200n*V(VCC,TACHINP), 0, 100n)
    *BITACHINN VCC TACHINN I=LIMIT(200n*V(VCC,TACHINN), 0, 100n) ; comment out for LM29x7_8
    **
    * Input stage with hysteresis
    Binschmitt 0 outschmitt1 I=0.5*(tanh((V(TACHINPX,TACHINN)-loth+(V(outschmitt1)-1)*(hith-loth))*1k)+1) ; non-inverting
    Rinschmitt 0 outschmitt1 1
    Cinschmitt 0 outschmitt1 100n
    *
    BV1 offsetschmitt1 0 V=V(vcc)/2*V(outschmitt1)+V(vcc)/4
    **
    * Charge pump stage
    B1 0 N001 I=0.5*(IUP+IDN)*(tanh(V(offsetschmitt1,pumpcap)*1k)+(IDN-IUP))
    Lconvfix1 N001 N002 1n ; unclear as to why but significantly improves convergence
    Rconvfix1 N001 N002 1G ; optional damping for Lconvfix1
    Vimon1 N002 PUMPCAP 0
    R1 PUMPCAP 0 1G
    C1 PUMPCAP 0 1f
    **
    * Pumpcap output rail clamps
    DPCAPVCCclamp PUMPCAP VCC Dclamp
    DPCAPGNDclamp 0 PUMPCAP Dclamp
    **
    * Charge mirror stage
    B2 0 N003 I=ABS(I(Vimon1)) ; I=uramp(I(Vimon1))+uramp(-I(Vimon1)) ; alternative ABS function
    R2 N003 0 1G
    C2 N003 0 1p
    **
    * Charge mirror output stage
    D1 VCC N004 Dclamp
    D2 N004 N005 Dclamp
    BCHGOP N005 0 I=LIMIT(400u*V(N005), 0, 200u)
    QCHGOP CHARGECAP N005 N003 PN
    R3 CHARGECAP 0 10Meg
    C3 CHARGECAP 0 1f
    **
    * Chargecap output rail clamps
    DCCAPVCCclamp CHARGECAP VCC Dclamp
    DCCAPGNDclamp 0 CHARGECAP Dclamp
    **
    * Opamp input resistances and rail clamps
    ROPINP OPINP 0 1G
    ROPINN OPINN 0 1G
    *DOPINPVCCclamp OPINP VCC Dclamp ; comment out for LM29x7_8
    *DOPINPGNDclamp 0 OPINP Dclamp ; comment out for LM29x7_8
    DOPINNVCCclamp OPINN VCC Dclamp
    DOPINNGNDclamp 0 OPINN Dclamp
    **
    * Opamp/comparator and floating output transistor stage
    * (modelled directly from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf)
    Q35 0 OPINN Q36B PN
    BIQ35E VCC Q36B I=LIMIT(6u*V(VCC,Q36B), 0, 3u)
    Q38 0 OPINP Q37B PN
    BIQ38E VCC Q37B I=LIMIT(6u*V(VCC,Q37B), 0, 3u)
    Q36 QD1C Q36B TAIL PN
    Q37 COMP Q37B TAIL PN
    BITAIL VCC TAIL I=LIMIT(12u*V(VCC,TAIL), 0, 6u)
    QD1 QD1C QD1C 0 NP
    Q39 COMP QD1C 0 NP
    Q40 0 COMP Q41B PN
    BIQ40E VCC Q41B I=LIMIT(6u*V(VCC,Q41B), 0, 3u)
    Q41 VCC Q41B Q41E NP
    Q42 Q41B Q41E Q43C NP
    Q43 Q43C Q41E 0 NP
    RQ41E Q41E 0 100k
    BIQ43C VCC Q43C I=LIMIT(100u*V(VCC,Q43C), 0, 50u)
    Q44 VCC Q43C Q44E NP
    CCOMP Q43C COMP 10p
    RQ45B Q44E Q45B 5k
    RQ45E Q44E EMITTER 15k
    Q45 COLLECTOR Q45B EMITTER NP
    **
    * Collector supply overvoltage and reverse voltage clamp
    * and emitter reverse voltage clamp
    DCOLLECTOR COLLECTOR 0 Drails
    DEMITTER 0 EMITTER Dclamp
    *
    .model PN PNP(BF=100)
    .model NP NPN(BF=100)
    *
    **
    * Models
    .model Dclamp D Is=1e-12 N=1 Rs=1
    .model Dclamp2 D Is=1e-12 N=0.1 Rs=1
    .model Drails D Is={iq} N=2 BV={7.56} IBV={iq*10} Rs=10.5 ; comment out for LM2907
    *.model Drails D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1 ; comment out for LM2917
    .model Dcollector D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1
    *
    .ENDS LM2917_8EE
    ***************************************************************************


    ***************************************************************************
    * LM2907 14 pin model
    *
    * Spice subckt of LM2917 in 14 pin package.
    * Developed for EasyEDA from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf
    * by signality.co.uk
    *
    * Last edited 150413
    **
    .SUBCKT LM2907_14EE TACHINP PUMPCAP CHARGECAP OPINP EMITTER NC1 NC2 COLLECTOR VCC OPINN TACHINN GND NC3 NC4
    RNC1 NC1 0 1T ; comment out for LM29x7_8
    RNC1 NC2 0 1T ; comment out for LM29x7_8
    RNC1 NC3 0 1T ; comment out for LM29x7_8
    RNC1 NC4 0 1T ; comment out for LM29x7_8
    *Vlink1 TACHINN GND 0 ; comment out for LM29x7_14
    *Vlink2 CHARGECAP OPINP 0 ; comment out for LM29x7_14
    .param IUP = 200u IDN = IUP
    + hith = 15m ; V. Upper threshold.
    + loth = -15m ; V. Lower threshold.
    + Vabsmax = 28 ; V. Absolute maximum supply voltage
    * Applies to VCC for LM2907 only and total across output
    * transistor or from COLLECTOR to GND for all devices.
    + iq = 3.8m-265u ; A. Quiescent current (less total of current sources).
    * Excldes current through zener on LM2917 devices.
    **
    * Quiescent current, supply zener and reverse voltage clamp
    *
    Diq_reverse_n_oversupply 0 VCC Drails
    **
    * Input resistances, rail clamps and bias currents
    RTACHINP TACHINP 0 1G
    RTACHINN TACHINN 0 1G
    DTACHINPVCCclamp TACHINP VCC Dclamp
    DTACHINPGNDclamp 0 TACHINP Dclamp ; comment out for LM29x7_8
    RSER TACHINP TACHINPX 10k
    *DTACHINPXGNDclamp1 TACHINPX 0 Dclamp ; comment out for LM29x7_14
    *DTACHINPXGNDclamp2 0 TACHINPX Dclamp2 ; comment out for LM29x7_14
    DTACHINNVCCclamp TACHINN VCC Dclamp ; comment out for LM29x7_8
    DTACHINNGNDclamp 0 TACHINN Dclamp ; comment out for LM29x7_8
    BITACHINP VCC TACHINP I=LIMIT(200n*V(VCC,TACHINP), 0, 100n)
    BITACHINN VCC TACHINN I=LIMIT(200n*V(VCC,TACHINN), 0, 100n) ; comment out for LM29x7_8
    **
    * Input stage with hysteresis
    Binschmitt 0 outschmitt1 I=0.5*(tanh((V(TACHINPX,TACHINN)-loth+(V(outschmitt1)-1)*(hith-loth))*1k)+1) ; non-inverting
    Rinschmitt 0 outschmitt1 1
    Cinschmitt 0 outschmitt1 100n
    *
    BV1 offsetschmitt1 0 V=V(vcc)/2*V(outschmitt1)+V(vcc)/4
    **
    * Charge pump stage
    B1 0 N001 I=0.5*(IUP+IDN)*(tanh(V(offsetschmitt1,pumpcap)*1k)+(IDN-IUP))
    Lconvfix1 N001 N002 1n ; unclear as to why but significantly improves convergence
    Rconvfix1 N001 N002 1G ; optional damping for Lconvfix1
    Vimon1 N002 PUMPCAP 0
    R1 PUMPCAP 0 1G
    C1 PUMPCAP 0 1f
    **
    * Pumpcap output rail clamps
    DPCAPVCCclamp PUMPCAP VCC Dclamp
    DPCAPGNDclamp 0 PUMPCAP Dclamp
    **
    * Charge mirror stage
    B2 0 N003 I=ABS(I(Vimon1)) ; I=uramp(I(Vimon1))+uramp(-I(Vimon1)) ; alternative ABS function
    R2 N003 0 1G
    C2 N003 0 1p
    **
    * Charge mirror output stage
    D1 VCC N004 Dclamp
    D2 N004 N005 Dclamp
    BCHGOP N005 0 I=LIMIT(400u*V(N005), 0, 200u)
    QCHGOP CHARGECAP N005 N003 PN
    R3 CHARGECAP 0 10Meg
    C3 CHARGECAP 0 1f
    **
    * Chargecap output rail clamps
    DCCAPVCCclamp CHARGECAP VCC Dclamp
    DCCAPGNDclamp 0 CHARGECAP Dclamp
    **
    * Opamp input resistances and rail clamps
    ROPINP OPINP 0 1G
    ROPINN OPINN 0 1G
    DOPINPVCCclamp OPINP VCC Dclamp ; comment out for LM29x7_8
    DOPINPGNDclamp 0 OPINP Dclamp ; comment out for LM29x7_8
    DOPINNVCCclamp OPINN VCC Dclamp
    DOPINNGNDclamp 0 OPINN Dclamp
    **
    * Opamp/comparator and floating output transistor stage
    * (modelled directly from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf)
    Q35 0 OPINN Q36B PN
    BIQ35E VCC Q36B I=LIMIT(6u*V(VCC,Q36B), 0, 3u)
    Q38 0 OPINP Q37B PN
    BIQ38E VCC Q37B I=LIMIT(6u*V(VCC,Q37B), 0, 3u)
    Q36 QD1C Q36B TAIL PN
    Q37 COMP Q37B TAIL PN
    BITAIL VCC TAIL I=LIMIT(12u*V(VCC,TAIL), 0, 6u)
    QD1 QD1C QD1C 0 NP
    Q39 COMP QD1C 0 NP
    Q40 0 COMP Q41B PN
    BIQ40E VCC Q41B I=LIMIT(6u*V(VCC,Q41B), 0, 3u)
    Q41 VCC Q41B Q41E NP
    Q42 Q41B Q41E Q43C NP
    Q43 Q43C Q41E 0 NP
    RQ41E Q41E 0 100k
    BIQ43C VCC Q43C I=LIMIT(100u*V(VCC,Q43C), 0, 50u)
    Q44 VCC Q43C Q44E NP
    CCOMP Q43C COMP 10p
    RQ45B Q44E Q45B 5k
    RQ45E Q44E EMITTER 15k
    Q45 COLLECTOR Q45B EMITTER NP
    **
    * Collector supply overvoltage and reverse voltage clamp
    * and emitter reverse voltage clamp
    DCOLLECTOR COLLECTOR 0 Drails
    DEMITTER 0 EMITTER Dclamp
    *
    .model PN PNP(BF=100)
    .model NP NPN(BF=100)
    *
    **
    * Models
    .model Dclamp D Is=1e-12 N=1 Rs=1
    .model Dclamp2 D Is=1e-12 N=0.1 Rs=1
    *.model Drails D Is={iq} N=2 BV={7.56} IBV={iq*10} Rs=10.5 ; comment out for LM2907
    .model Drails D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1 ; comment out for LM2917
    .model Dcollector D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1
    *
    .ENDS LM2907_14EE
    ***************************************************************************


    ***************************************************************************
    * LM2917 14 pin model
    *
    * Spice subckt of LM2917 in 14 pin package.
    * Developed for EasyEDA from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf
    * by signality.co.uk
    *
    * Last edited 150413
    **
    .SUBCKT LM2917_14EE TACHINP PUMPCAP CHARGECAP OPINP EMITTER NC1 NC2 COLLECTOR VCC OPINN TACHINN GND NC3 NC4
    RNC1 NC1 0 1T ; comment out for LM29x7_8
    RNC1 NC2 0 1T ; comment out for LM29x7_8
    RNC1 NC3 0 1T ; comment out for LM29x7_8
    RNC1 NC4 0 1T ; comment out for LM29x7_8
    *Vlink1 TACHINN GND 0 ; comment out for LM29x7_14
    *Vlink2 CHARGECAP OPINP 0 ; comment out for LM29x7_14
    .param IUP = 200u IDN = IUP
    + hith = 15m ; V. Upper threshold.
    + loth = -15m ; V. Lower threshold.
    + Vabsmax = 28 ; V. Absolute maximum supply voltage
    * Applies to VCC for LM2907 only and total across output
    * transistor or from COLLECTOR to GND for all devices.
    + iq = 3.8m-265u ; A. Quiescent current (less total of current sources).
    * Excldes current through zener on LM2917 devices.
    **
    * Quiescent current, supply zener and reverse voltage clamp
    *
    Diq_reverse_n_oversupply 0 VCC Drails
    **
    * Input resistances, rail clamps and bias currents
    RTACHINP TACHINP 0 1G
    RTACHINN TACHINN 0 1G
    DTACHINPVCCclamp TACHINP VCC Dclamp
    DTACHINPGNDclamp 0 TACHINP Dclamp ; comment out for LM29x7_8
    RSER TACHINP TACHINPX 10k
    *DTACHINPXGNDclamp1 TACHINPX 0 Dclamp ; comment out for LM29x7_14
    *DTACHINPXGNDclamp2 0 TACHINPX Dclamp2 ; comment out for LM29x7_14
    DTACHINNVCCclamp TACHINN VCC Dclamp ; comment out for LM29x7_8
    DTACHINNGNDclamp 0 TACHINN Dclamp ; comment out for LM29x7_8
    BITACHINP VCC TACHINP I=LIMIT(200n*V(VCC,TACHINP), 0, 100n)
    BITACHINN VCC TACHINN I=LIMIT(200n*V(VCC,TACHINN), 0, 100n) ; comment out for LM29x7_8
    **
    * Input stage with hysteresis
    Binschmitt 0 outschmitt1 I=0.5*(tanh((V(TACHINPX,TACHINN)-loth+(V(outschmitt1)-1)*(hith-loth))*1k)+1) ; non-inverting
    Rinschmitt 0 outschmitt1 1
    Cinschmitt 0 outschmitt1 100n
    *
    BV1 offsetschmitt1 0 V=V(vcc)/2*V(outschmitt1)+V(vcc)/4
    **
    * Charge pump stage
    B1 0 N001 I=0.5*(IUP+IDN)*(tanh(V(offsetschmitt1,pumpcap)*1k)+(IDN-IUP))
    Lconvfix1 N001 N002 1n ; unclear as to why but significantly improves convergence
    Rconvfix1 N001 N002 1G ; optional damping for Lconvfix1
    Vimon1 N002 PUMPCAP 0
    R1 PUMPCAP 0 1G
    C1 PUMPCAP 0 1f
    **
    * Pumpcap output rail clamps
    DPCAPVCCclamp PUMPCAP VCC Dclamp
    DPCAPGNDclamp 0 PUMPCAP Dclamp
    **
    * Charge mirror stage
    B2 0 N003 I=ABS(I(Vimon1)) ; I=uramp(I(Vimon1))+uramp(-I(Vimon1)) ; alternative ABS function
    R2 N003 0 1G
    C2 N003 0 1p
    **
    * Charge mirror output stage
    D1 VCC N004 Dclamp
    D2 N004 N005 Dclamp
    BCHGOP N005 0 I=LIMIT(400u*V(N005), 0, 200u)
    QCHGOP CHARGECAP N005 N003 PN
    R3 CHARGECAP 0 10Meg
    C3 CHARGECAP 0 1f
    **
    * Chargecap output rail clamps
    DCCAPVCCclamp CHARGECAP VCC Dclamp
    DCCAPGNDclamp 0 CHARGECAP Dclamp
    **
    * Opamp input resistances and rail clamps
    ROPINP OPINP 0 1G
    ROPINN OPINN 0 1G
    DOPINPVCCclamp OPINP VCC Dclamp ; comment out for LM29x7_8
    DOPINPGNDclamp 0 OPINP Dclamp ; comment out for LM29x7_8
    DOPINNVCCclamp OPINN VCC Dclamp
    DOPINNGNDclamp 0 OPINN Dclamp
    **
    * Opamp/comparator and floating output transistor stage
    * (modelled directly from datasheet:
    * www.ti.com/.../lm2907-n.pdf
    * and apps note:
    * www.ti.com.cn/.../snaa088.pdf)
    Q35 0 OPINN Q36B PN
    BIQ35E VCC Q36B I=LIMIT(6u*V(VCC,Q36B), 0, 3u)
    Q38 0 OPINP Q37B PN
    BIQ38E VCC Q37B I=LIMIT(6u*V(VCC,Q37B), 0, 3u)
    Q36 QD1C Q36B TAIL PN
    Q37 COMP Q37B TAIL PN
    BITAIL VCC TAIL I=LIMIT(12u*V(VCC,TAIL), 0, 6u)
    QD1 QD1C QD1C 0 NP
    Q39 COMP QD1C 0 NP
    Q40 0 COMP Q41B PN
    BIQ40E VCC Q41B I=LIMIT(6u*V(VCC,Q41B), 0, 3u)
    Q41 VCC Q41B Q41E NP
    Q42 Q41B Q41E Q43C NP
    Q43 Q43C Q41E 0 NP
    RQ41E Q41E 0 100k
    BIQ43C VCC Q43C I=LIMIT(100u*V(VCC,Q43C), 0, 50u)
    Q44 VCC Q43C Q44E NP
    CCOMP Q43C COMP 10p
    RQ45B Q44E Q45B 5k
    RQ45E Q44E EMITTER 15k
    Q45 COLLECTOR Q45B EMITTER NP
    **
    * Collector supply overvoltage and reverse voltage clamp
    * and emitter reverse voltage clamp
    DCOLLECTOR COLLECTOR 0 Drails
    DEMITTER 0 EMITTER Dclamp
    *
    .model PN PNP(BF=100)
    .model NP NPN(BF=100)
    *
    **
    * Models
    .model Dclamp D Is=1e-12 N=1 Rs=1
    .model Dclamp2 D Is=1e-12 N=0.1 Rs=1
    .model Drails D Is={iq} N=2 BV={7.56} IBV={iq*10} Rs=10.5 ; comment out for LM2907
    *.model Drails D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1 ; comment out for LM2917
    .model Dcollector D Is={iq} N=2 BV={Vabsmax+1} IBV={iq*10} Rs=1
    *
    .ENDS LM2917_14EE
    ***************************************************************************
  • 0 in reply to Andy Fierman
    Prodigy 20 points
    Hi,
    I tried to simulate this model using TINA-TI tool, but it shows an error 'missing number . on line #19' cannot generate circuit.
    The one on allaboutcircuits.com also has an error. Please see if it can be corrected.

    Thanks and Regards,
    Deepika R
  • 0 in reply to deepika r27
    Prodigy 40 points

    Hi Deepika,

    It is possible that the error you see is in the subckt line:

    .param IUP = 200u IDN = IUP

    and that rewriting the line to:

    .param IUP = 200u IDN = {IUP}

    or:

    .param IUP = 200u

    + IDN = {IUP}

    may fix your error.

    However, I did say about the family of spice models for the LM2907-8, LM2917-8, LM2907-14 and LM2917-14 devices that I posted up here:

    "They are written for ngspice but should run unaltered in LTspice and Pspice."

    They are not written for TINA-TI and, as I have not studied the syntax of TINA, I am unable to help you translate them from their native ngspice other than to suggest you have a look at:

    https://e2e.ti.com/support/development_tools/webench_design_center/f/234/t/94725

    The models I posted run natively in the free web-based EasyEDA tool and also run in LTspice.

    The models that the link to allabout circuits points to are clearly described as having been written for, and indeed do run in, LTspice.

    It is possible that they use LTspice specific models and syntax that ngspice, Pspice or TINA-TI do not understand.

  • 0 in reply to Andy Fierman
    Prodigy 20 points
    Hi Andy,

    Thank you, but that did not help.
    TINA doesn't seem to accept .param and also its possible there are lot of syntax mismatch, because the macromodel did not complie and I do not understand those errors.
    But making it work for TINA tool would be halpful. I will check the model with LTSpice.

    Thanks,
  • 0 in reply to deepika r27
    Prodigy 40 points

    Hi Deepika,

    If you need to end up with a PCB for the circuit in which you are using the LM2907 then you might be better off just using EasyEDA. 

    It already has schematic symbols, spice models and suitable PCB footprints for all the LM29xx variants.

    :)