INA126: Too low gain

Hello Soren,

Can you provide us with the INA126 circuit schematic showing how the RTD connects to the inputs, the supply voltage(s) and what is connected to the output? That information could prove helpful in diagnosing the problem.

Regards, Thomas
Precision Amplifiers Applications Engineering

Hello Thomas

Hier is a part of the schematic. U10 is okay and U12 has measuring issue.

schcut.pdf

I hope you can see the schematic. Here it just indicates that something is attached/inserted.

Regards Soren

Hi Soren,

aren't the 47k protection resistors a bit too high in combination with the rather high input bias currents of INA126 of up to 50nA? This gives huge measuring errors.

Kai

Hello Soren,

Reviewing the schematic and signal paths it appears that the INA126 at U10 and the one at U12 should have the same gain of 5.08 V/V, but something is corrupting the gain of U12. When you measure the gain for U10 and U12 is it with respect to the output pin 6, in each case? The minimum INA126 gain of 5 V/V is established by the internal resistors and very high open-loop gain of the op amps used in this instrument amplifier configuration. For the gain to drop below 5 V/V to 4.6 V/V would mean that a change in an internal resistor(s) or gain set resistor RG would be required.

Since you are noticing a change in the U12 gain over time, and a difference in the static dc resistance between IN- (pin 2) to REF (pin 5) for the two devices, there may be a PC board solder flux contamination issue at work. What is your PC board cleaning procedure?

Did you acquire the INA126 devices from TI, or a TI authorized distributor?

Regards, Thomas
Precision Amplifiers Applications Engineering

Hi Kai

I have thought about that myself and have tried to short-circuit these resistors, but this did not make any difference in the measurements.

/Soren

Hello Thomas

Measurements of outputs have been made with respect to the reference.
No flux contamination has been found and the components are purchased through either Arrow or Avnet.

Can you recommend er test setup for INA 126?

Regards, Soren

Hi Soren,

hmm, I have no idea what could be the cause of gain error. The circuit looks good, apart from the too high 47k current limiting resistors.

Could it be a defect of components? Due to overheating during the soldering? Or was the PCB bended or sagged too much? Or sees the PCB heavy vibration?

Another issue could be the multiplexing sequence. Is the multiplexers given enough time so that the signal can fully settle at the outputs of INA126? There is heavy low pass filtering in the signal path. Have you considered that?

I would divide the circuit into individual test portions and test portion for portion. Are you sure that it is a true gain error of INA126? Or could it be a input bias current drift or offset voltage drift? For a gain measurement you need at least two measuring points. By the help of these two measuring points you can calculate the true offset and true gain. You have you done it this way or only taken one measuring point? Can you elaborate a bit how exactly you have measured the gain error?

Kai

Hello Soren,

I do think it could prove a helpful exercise to evaluate U10 and U12 outside of the schcut.pdf circuit board. The INA126 Figure 18, Basic Connections circuit shown on datasheet Pg. 12 should be easy and straightforward to apply as a test circuit.

Use the same RG value of 1 Megohm, and an RL of 24 k, or 25 k. Make sure the resistor used for RG is a precision resistor. Add the 5.1 k resistors to each input, and ground the opposite end of the one connected to the INA126 -IN input. Initially, drive the 5.1 k associated with the +IN input with a precise voltage and checkif the gain is 5.08 V/V. Then, add a 47 k in series with the +IN 5.1 k resistor and recheck the gain. Run these tests for both of the U10 and U12 devices and confirm you obtain the same results for each of them.

If these checks result in an accurate +5.08 V/V gain in all test cases, then there is something else on the remainder of the board that is causing the gain error.

Regards, Thomas
Precision Amplifiers Applications Engineering

Hi Kai

I have fixed the multiplexer position and the issue is still there.

I had 2 measuring points, one in each end of the scale, but I have realized I have been unfourtunate that the gain calculation in both cases gav about 4.6.
A test with shorted inputs on INA126 gav an output of -0.473V from the component. This made me redo my measurements and take additional measurements. Taking the offset into account all masurements resulted in a gain of 5.08, exept for an input of about 100mV gain was 4.7.

I got some INA126 which have been changed on failing products and made a test setup with inputs and reference pin shorted together and measure the output. Failling components output was measured from -140mV to -1.35V. OK components output was measured from 0 to -1.9mV.

You was right it was a 'defect' component.

Regard, Soren

Hi Thomas

As you can see in my reply to kai klaas69, my issue is in reallity a large offset and not a gain error.

Now I hope you can help me to make a good protection of the circuit so I hopefully will not see this problem again.
Some of the components is okay to begin with and later on this offset comes and corrupt the measurements.
My first thougt was ESD, but I have tried to recreate the phenomena without success.

Do you have any idea how the INA126 can be 'damaged' and get a offset?

Regards, Soren

Hi Soren,

the INA126 cannot withstand much ESD. It's only 500V when you take a look into the datasheet. So, even sounding rather improbable ESD could have damaged the INA126. This can be seen sometimes, if the layout is large and no solid ground plane is used. Then, ESD running over the whole PCB can create large and destroying common mode voltages within the circuit. In this case the INA126 will not profit very much from the 47k current limiting resistors at the inputs of multiplexers or even the protection circuitry at the PT100 input.

I would add a solid ground plane to the PCB and would shunt ESD entering the PT100 inputs directly to chassis ground via hybrid grounding (a 10...100n cap from signal ground to chassis ground). Don't ever allow ESD running through your circuit. Always shunt ESD to the chassis ground. I have noticed that you have C406 in your circuit. But with so many PT100 inputs and so many TVS in your circuit you might need many more of these caps to minimize the ESD current path lenghts from signal ground to chassis ground. Remember, when it comes to ESD every millimeter counts!! One C406 alone is not enough at all!!!

Also, I would use a shielded cables for the PT100 and connect the cable shields directly to chassis ground with 360° bonding.

Kai

Hi Soren,

you also might want to have a look at this thread:

e2e.ti.com/.../2620445

Kai

Hi Soren again,

just noticed that you have 33V TVS at the PT100 inputs. Why such a high turn-on voltage?? I would take TVS with much lower turn-on voltage.

Kai

Hello Soren,

Understanding and resolving what is inducing the INA126 high offset could be a difficult issue to resolve. First off, we need your assurance that the INA126 devices were obtained directly from TI, or a TI authorized distributor. If that is the case, the product would have been assembled, handled, tested and packaged following strict ESD procedures, and strict compliance requirements in place. If ESD damage is the issue, then I would expect that it would had to have occurred sometime after the devices were removed from their the ESD protective packaging in which they were packaged and shipped.

If the INA126 devices were still undamaged after being installed in the PC board, then an in-circuit ESD or Electrical Overstress (EOS) event would be the only mechanisms that would explain subsequent electrical damage. Normally, a very high series input resistance of 5.1 kilohms, or 47 kilohms will go a long way in limiting the input current that might be forced to flow during an ESD, or EOS event. The voltage level associated with the event would have to be very high to result in damaging input current levels. In the event of an out-of-circuit ESD event where the duration of the event is very limited in time, the ESD cells and internal absorption device would become activated and dissipate the power associated with the event. However, if the ESD voltage exceeds the +/-500 V HBM rating, then the cells or internal circuits could be damaged. There is also the possibility of a CDM ESD condition, which isn't specified for the INA126 but might occur. In either case ESD damage could explain the high offset.

In-circuit EOS events occurring at the device inputs, supply pins or output can result in device damage. If there is the potential for EOS, then we often recommend the inclusion of transient voltage suppressors (TVS) at the circuit points where the EOS occurs. TVS devices used at the input of instrumentation amplifier such as the INA126 are different than the TVS devices used at the power supply pins. The input protection needs to exhibit low capacitance and low leakage current as to have little effect on the active circuit performances. Companies such as Littelfuse make a variety of TVS protection devices. Here is a link to such a device:

They also produce TVS devices suitable for power supply pin protection. TI has no affiliation with Littelfuse, and I provide this reference for informational purposes only. Please contact them for assistance with their TVS products.

Regards, Thomas

Precision Amplifiers Applications Engineering