OPA4348: Differential amplification circuit

Well you obviously ringing LIn, 

That is due to the feedback pole introduced by the higher R values to the inverting input C in the model

You can tune that out with a C across the feedback R matching that with the same value across the R to ground at the input. 

Lin,

In your simulation the two inputs are [0V and +200V levels] and not [-200V and +200V]. The common mode is effectively +100V and the input difference is +100V and -100V. 

Is the goal to measure the common mode signal or the difference signal?

Hi Michael,

Thank you for your help here. I tried a 100pF capacitor across the V+ to GND and V- to Vo. The output is still almost the same. Could you share with me more solutions to solve it? Thanks. 

Hi Ronald,

I want to measure the common-mode signal as VG1 and Vin shows. Thanks. 

Well Lin,there might be a number of things going on here - you did not attach a TINA file, but here is part of your ckt running just the inverting channel - few things here. 

1. The online models for the OPA348 and OPA4348 have the supplies reversed from you snip, where did you get that model? Actually, I also just checked in the V11 library, and yes there is that model with the supply polarity you show.That is a 2003 model vs the current 2011 model online. Not sure which is better and not going to check now. 

2. I went to +/-2.5V supplies, if you are running into 0V on the V+ input, be careful about running into ground onthe output pin - it cannot swing to ground exactly. 

3. Running just inverting shows that peaking I would expect due to the high R values, about 15dB peaking, pretty poor. 

Here is the header for the netlist for the model I think you are using, 

So, in any case, lets set your ckt up for LG phase margin with the current web folder model, And probe the feedback voltage across the inputs with the parasitics in place, gives about 18deg phase margin - yes, you should be ringing - incidentally, it was critical to add the V+ input Ccm here to get this result. 

And adding a 3pF across the feedback to kind of match the Ccm onthe inverting input, yes works pretty well, 38deg phase margin now, Anyway, this LG file is below, you can play with it to get better PM, but I need to move on for now, 

And the file, I just noticed a mistake above, that R8 should be 42.3M, don't think it will change things much, but making that change in my file made eveything wors, so make that change before you start tuning. 

OPA348 diff attenuator LG.TSC

One more step, I took the peaking closed loop sim and just added a 3pF across the feedback - looks pretty good now, here is the file and sim below

OPA348 diff attenuator closed loop.TSC

Lin,

This circuit will measure the common mode input voltage (A+B)/2/100 where A & B are the two input voltages. The gain is 1/100

Here is the simulation result.

The input is always 0V and 200V, the common mode is 100V. The gain is 1/100, the output voltage is 1V

The 1M resistors should be made of a series chain of smaller resistors; for example five 200k resistors. 

Hi Michael,

Thank you for the explanation. I am sorry that I did not attach the right TINA file, see the file attached. The previous model comes from the TINA library, I have used the updated model. The result is below, the output has 1mV ripple, what is the main reason cause this ripple? Also, I have done some test on hardware, see waveform below, 

Test waveform in TINA

CH1 VG1 to GND

CH2 V+ to DGND

CH3 V- to DGND

CH4 Output to DGND

M CH2-CH3

As you can see, in the hardware test result, the CH2-CH3 Vpp is about 254mV, which means V+ is not equal to V-, this will cause higher offset voltage and let the output Vpp about 200mV. I suspect that this is related to CMRR is decreasing when noise signal frequency becomes higher. How about your opinion? 

If so, do you have some other opamps solution that can solve this problem? Thanks. 

OPA4348 common mode simulation.TSC

Lin,

The output ripple levels are 3mV & 4mV. For all practical purposes both are 0V ground. Is a zero output really what you wanted? I have to admit that I don't fully understand the goal of the circuit. A math equation would be a clear answer. I assumed goal was (A+B)/2*Gain where A & B are two inputs and Gain is unspecified so far.

Hi Ronald，

Thank you for your response here. The customer uses this circuit to measure inverter bus high voltage, about 200-400V, the AMP reference point is float GND, based in the middle of the bridge. When inverter works, the float GND will change frequently, this is why I want to simulate this circuit. The simulation result may not be aligned with the result we test in the customer system, so I may need our team's help to understand the reason. Thanks. 

BR,

Charles 

Hi Lin,

in your last TSC-file are at least two drawing mistakes. And all your posts are very hard (read impossible) to decipher...

Can you show the original schematic? And would it be possible to describe the problem in more than only two sentences?

Kai

Hi all,

Thank you for all your help here. The customer cannot share the schematic with me, so I draw the schematic below. They use the below circuit to measure high voltage, about 400V, and when the fault happened, such as B+ is short to GND, the V+ is not equal to V-, see waveform below. The customer wants to know the main reason, I am guessing if this is related CMRR? Hoa bout your opinion? 

Also now I am not clear who should be responsible for this thread? Thanks. 

CH1 B+ to GND

CH2 V+ to DGND

CH3 V- to DGND

CH4 Output to DGND

M CH2-CH3

Lin,

Consider that a 42.3M ohm resistor and the 6pF common mode input capacitance has a cutoff freq of 627 Hz. If you really want the diff amp to work with a 5 kHz carrier, make the circuit frequency neutral. Even with that, there will be a limit of CMRR mostly due to the matching of the resistors. If capacitors are added then their matching will also affect CMRR.    

Hi Ron,

Thanks. Do you know what is the effect to CMRR when matching of the resistors higher or lower? I would appreciate it if you can share with me some formula to calculate it? 

BR,

CL

Hi Lin,

first, take care, your measurements become kind of unrealistic when you touch with the probe the V- pin of circuit, since this is the inverting input of OPAmp and adding probe capacitance can result in ringing or even instability. Or by other words, by probing you even increase the imbalance of your differential amplifier. This could be the cause why the "M" curve looks so spiky.

Then, it's impossible to ideally balance the simple 1-OPAmp differential amplifier topology. You would need to take the 3-OPAmp topology. Only this topology will presents equal input impendances. But even then, manufacturing tolerances, temperature drift and long term drift will ruin the symmetry. As a rule of thumb, using 1% resistors give a common mode rejection of no better than 40dB. 0.1% resistors yield about 60dB. Due to long term drift, trying to achieve more is not realistic, even not with careful adjustments. And to balance the input filtering caps is critical as well, as Michael already mentioned.

The next issue is the common mode rejection of the OPAmp itself. Figure 2 of datasheet shows the common mode rejection versus frequency. It can be seen that at higher frequencies the common mode rejection drastically decreases. This means that even a perfect match of external components would no longer help.

I think, the real problem is that you want to reject the common mode noise which is dropping across the Y-cap. This common mode noise can directly come from hell without any bandwidth limitation and without any limitation of amplitude. Everything will drop here from ESD over Burst to even Surge. I don't think that an OPAmp circuit will be able to reject this properly. And the OPA4348 is even way too slow for this task.

I would recommend to use an isolation amplifier with the "dirty" GND of your scheme connected to the input side and the "clean" DGND connected to the output side.

Kai

Hi Lin,

what do you think about using an isolation amplifier?

Kai

Lin,

I also like Kai's idea for an isolation amplifier. The isolation is great for common mode mode rejection.

Hi Lin , you can try modifying the high side low cost current sensing method shown in the TINA file attached .high side sensing.TSC

You need to use a transistor with high enough VCE for such a circuit above .

What is the slew rate of the switching signal ? i.e how much time does it take to go from -200 to +200 during the transition .

This number will help us understand what type of CMRR might be required by your opamp circuit .

For DC common mode voltage the CMRR to resistance tolerance is given below .