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OPA4348: Power on circuit output has 6.5ms overshoot, do not know what caused?

Part Number: OPA4348

Power on circuit output has 6.5ms overshoot, do not know what caused? Please help me analyze.

Power supply: 24 v-dcdc-5 v-ldo-3.3 V

5V reference chip 3v-1.5v VREF

  • Hi Carl,

    allow the OPAmp some time to stabilize after power-on. So a bit overshot is totally normal after power-on.

    If the overshot is lasting longer, time constants formed by the Rs and Cs in the circuit can be the cause. Unfortunately, I cannot see any component values in your schematic. So it's impossible for me to give a more concrete answer :-(

    C14 and C20 are dangerous. They erode the phase margin and you risk instability.

    Can you post a full schematic? The more details, the more help :-)

    Kai

  •  The parameters of each component of the circuit are shown in the figure below. During the test, the rear end of adial is connected to the rear stage, and there is no other load, so it directly enters the MCU AD sampling pin.

  • Hi Carl,

    120k and 100nF low pass filter forms a time constant of 12ms. So I think the overshot can only be decreased by decreasing this time constant.

    Unfortunately, there's another issue. Your circuit isn't stable. The phase margin is only 26°:

    carl_opa4348.TSC

    Kai

  • Hi Carl again,

    I would remove the 1n cap (C20) and add this snubber :-)

    carl_opa4348_1.TSC

    Kai

  • Former Member
    0 Former Member in reply to Carl Shen

    Hi Carl,

    Please let us know if you are able to implement Kai's techniques and whether they have alleviated your issue to any extent.  Do you see problems at other times of operation?  As Kai has mentioned, it is possible that there will be some overshoot at the output during power on.  I would also recommend removing C20 and C14 and considering Kai's snubber suggestion.  Capacitors tied across the inputs tend to cause stability issues.

    Hi Kai,

    Thank you very much for your assistance with this question!

    Regards,
    Daniel

  • Former Member
    0 Former Member in reply to Carl Shen

    Hi Carl,

    One more thing I should have mentioned: once you decide on your circuit, it is a very good idea to check the stability of both stages independently to make sure both are stable. 

    The first stage will require a more complex procedure, as shown by Kai below.  You can copy his circuit or learn more about the method from Tim Green's presentation, "Dual FB Beta_plus and Beta_minus RevD.pptx".  The second stage is more simple and can be done using the method shown in TI Precision Labs on op amp stability.

    Please let me know if you have any further questions on this.

    Regards,
    Daniel

  • Former Member
    0 Former Member in reply to Carl Shen

    Hi Carl,

    It's been a while since we last heard from you and I am going to assume your issue has been resolved.  I hope that is indeed the case.

    Please let me know if you need anything else.

    Regards,
    Daniel