Morning Fairuz

Conceptually this should be ok, comments 

1. The THS4032 is a very low voltage noise dual channel device, you have degraded that with the 1kohm feedback R (4nV at 25C). 

2. Depending on your signal dynamics (speed and swing) the net load might start to appear pretty heavy here, be sure to run some LG phase margin sims. 

3. Very few ADC's need the high swing provided by the THS4032 with its higher supply range, there are many lower supply options today on single 5V or +/-5V supplies. 

Hi Fairuz,

it also depends on the ADC. What ADC are we talking about?

But why do you want to read an identical input signal by four ADC channels?

Kai

Hi Kai, this is for 12 bit SARADC. the reason we have 4 identical input as this is for ATE testing (1 DUT may have multiple ADC input), thus need to save space on test board (which we have other component allocation, this circuit will be replicated to test 60 DUT). Other engineer did mentioned I may degrade signal during ADC sampling. however to add more op-amp may require additional space. any suggestion appreciated.

Well the question if this is ok is way too vague, 

1. What supplies on the op amp? might want to be concerned about DUT overdrive, if you are using +/-12V for instance on the op amp, that is very possible

2. If you constrain your op amp solution so something that cannot break your DUT input range, that is probably going to be a RRout device - look at at the OPA837 for instance, 

3. Most SAR's are differential input? but if you have a single ended ASIC fine, 

4. What are you testing, DC linearity or SAR dynamics - that then gets into noise and HD through the SAR. 

Hi Michael,

1. we are using -3 to 12V supply to the opamp from ATE resource.

2. DUT SARADC input range 0-5V, and at least few room needed. OPA837 seems not suitable with the test range I have.

3. yes this is single ended SARADC.

4. DC linearity only, no dynamic test. Anyhow, the SARADC is rated 20KHz bandwindth.

if multiple ADC input is not recommended from single op-amp, is there any other option ie any other buffer circuit for the SARADC with small footprint? I have space contrain on ATE board, looking for alternative with minimize footprint.

Fairuz

Morning Fairuz, thanks for the detail, 

Many different op amps might be suitable to this need - parallel driving is normally no problem as long as stability is assured.

Your supplies are relatively high to satisfy the high headroom for this very old THS4032 solution, but it is stable - you do risk overdrive damaging your DUT. 

Here is an Aol sim adapted to your THS4032 design, very good 53deg phase margin. 

Here is this sim file, 

THS4031 LG sim driving 4 loads.TSC

I did not do an exhaustive search for an alternate device that might produce your 0 to 5V swing for DC testing, but here is one option with minimal chance of overdrive damage and much better DC - it is actually lower phase margin, but at 28deg still ok. Use the LM7705 to get that negative 0.23V for negative supplies. WIth 5.2V positive supply, still under the 5.5V maximum and there is no chance of overdriving the SAR inputs to the point that you turn on the ESD diodes. This will be much slower, higher noise, solution - but lower power and more accurate DC wise. I used a zero crossover device since you are running as unity gain buffer and did not wan the input crossover problems of more typical RRinput devices. I also reduced your feedback to 100ohm and added the 9pF input parasitic at the V- node for this loop gain sim. 

Here is this file, 

OPA325 LG sim driving 4 loads.TSC

Hi Michael, Thanks, i think the phase margin will be ok. My other worry is will the voltage degrade too much at the SARADC input during sampling since it has multiple sharing. i will make another research on this.

Hello Fairuz,

Can you clarify what ADC you are using here exactly? Is the ADC simultaneously sampling or does it have an internal mux to switch between channels?

Best,

Hasan Babiker

Hi Hasan, its SARADC with 1 input. 20kHz, 1MSPS. ultimate goal is to test all ADC simultaneously, but  signal may degrade during sampling. worse case will add relays before filter and test sequential which will incur more time. if there is suggestion on simultaneous test, will be appreciated.

Hello Fairuz,

I agree there may be some signal degradation especially if the clocks on the ADCs aren't synced. Wasn't quite clear to me if you are using a multi-channel ADC here or using multiple but if signal doesn't meet your performance requirements you may want to look into a switching to a multi-channel. I believe there are some with both internal muxes to switch between channels & also simultaneous sampling.

Best,

Hasan Babiker