Hello team,
Could you please provide the output voltage swing (Vo) value for larger RL such as RL>1MOhms?
I'd appreciate if you provide the RL vs VO plot.
I'd like to check this in order to consider the limitation of rail to rail system.
The output goes to high impedance input, so I'd like to check the performance.
Regards,
Itoh
Figure 10 does not go down to 0 mA. But extrapolating the lines implies that the device can reach the ±2.75 V rails.
The datasheets of similar devices like the TLV9002/TLV9042/TLV9052 do show 0 mA, and have a voltage drop of 0 V at this point.
The ADC's analog input has a capacitance of 30 pF; the datasheet says that it "will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance." The TLV9062 is such a low-impedance source.
The ADC's analog input has a negligible leakage current, so the TLV9062 will be able to output voltages at the rails.
The only possible problem is with high-frequency signals, because at the most extreme voltages, the TLV9062's output will not be able to (dis)charge the sampling capacitance as fast. See image 30, and note that it was measured with a load of 10 pF:
What frequencies are you using?
I am not a TI employee, and that graph shows typical values. The knee for 3.3 V appears to be somewhere near 166 kHz.
Is 166 kHz the sampling frequency or the signal frequency? Slower signals would work fine.
If you need to handle 166 kHz signals, you should use an opamp with a higher slew rate, e.g., OPA2322 or OPA2320:
Dear Aramaki-san,
The plot for the TLV9062 at 3.3V would look like the blue line below.
As you can see, this is about mid-way between 100kHz and 1MHz on the logarithmic scale. This corresponds to 316kHz. We can also determine this using the formula below.
Using this equation and the typical value for the slew rate of this part, we get a full-power bandwidth of about 313kHz. So, your circuit will have the speed to provide the full output voltage swing at up to 313kHz. Keep in mind that this assumes a few things:
1. This is valid for a sinusoidal plot.
2. There is no heavy capacitive load. Heavy loads may affect settling time.
3. This uses the typical value for the slew rate. In the real-world, there will be some variation of this value. So, it is a good idea to leave some margin.
4. Most importantly, this does not take into account the output swing from the rail limitation. This only accounts for speed and not output current/headroom capabilities.
Also, Clemens has asked a good question: is this the sampling frequency or the signal frequency?
Please let me know if you have any further questions.
Regards,
Daniel Miller
Dear Aramaki-san,
I am happy to help. As a final piece of advice, I would say that the general recommendation for amplifier speed is 40dB of margin between the open-loop bandwidth curve and the maximum frequency of interest into the op amp. This is explained in detail in this app note (click here for link) and is summarized at the bottom of page 7.
For example, the open-loop gain curve of the TLV9062 is below in red. A gain of 24.5V/V corresponds to 27.8dB of gain. So, with 40dB of margin, we would want about 67.8dB of gain in the open-loop curve at 4kHz (assuming this is the maximum input frequency of interest). You can see that the TLV9062, which has a 10MHz bandwidth, seems to meet this metric.
I hope our answers were clear. Please let us know if further help is needed.
Regards,
Daniel Miller
