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PCM1795: 32bit-I2S for PCM1795

Takeo Ootsuka
Prodigy 10 points
Part Number: PCM1795

Hi.

I'm using PMC1795 set to 32bit-I2S mode.(fs=128 BCK、FMT[2:0]=100)

I2S has the same data start position for both 24bit and 32bit in datasheet.

But, in actual operation, 32-bit I2S is in the right-justified position.

I've read the datasheet several times in search of something that could explain this behavior, but I can't understand it.

Is the datasheet wrong?

Best regard.

  • 0
    TI__Guru 53633 points

    Hi Ootsuka-san,

    Can you clarify your question? The PCM1795 expects the data to be left justified, even if there are extra BCK periods before the next LRCK edge.  What is your I2S host outputting?

    Thanks,

    Paul

  • 0 in reply to Paul_Frost
    Prodigy 10 points

    Thank you for reply.

    The I2S host supplies LRCK with sampling period, BCK=128fs, and SCLK=256fs.(duty=50)

    The data outputs sine wave data with a delay of 1 BCK from LRCK edge, and a fixed value (0xAAAA-AAAA) is output to the invalid data section.

    A sine wave is output when 24bit-I2S is set. But a fixed level is output when 32bit-I2S is set.


    I don't understand what's going on.

    What's happening?

  • 0 in reply to Takeo Ootsuka
    TI__Guru 53633 points

    Hi Ootsuka-san,

    This both of these formats should be okay with this device.  They are both supported.  Can you confirm with an oscilloscope that the I2S format is still correct when the mode is changed? Are both channels not working, or just one?

    This is a strange format - why are you using BCK=128×fS?

    Thanks,

    Paul

  • 0 in reply to Paul_Frost
    Prodigy 10 points

    Thank you, Mr.Frost.
    I measured the waveform with an oscilloscope.
    The state of the right channel is the same.

    • zero output

    <I2S-24bit>

    <I2S-32bit>
      • sine output(left channel)

      <I2S-24bit>

      <I2S-32bit>
        •  0x7FFF-8000 output. (Left channel)

        <I2S-24bit>

        <I2S-32bit>

        CH1:current to voltage converter output
        CH2:DATA
        CH3:LRCK
        CH4:BCK

        The invalid data was 0x5555-5555.(Invalid data is added to investigate the cause.)
        I'm sorry for making a mistake.

        There is no reason to use BCK=128xfs.
        Of course, it is possible to use it with BCK=64xfs.
        But before that, I want to figure out the cause.

        Best regard.

      • 0 in reply to Takeo Ootsuka
        TI__Guru 53633 points

        Hi Ootsuka-san,

        Is it possible that your I2S host is left shifting the data when you set the output to be 32 bit? From your sine wave example, it does not look like there is valid data in the most significant 8 bits:

        This could just be the specific code that that was being sent, but it would be worth checking to confirm if you see a very low amplitude sinewave on the output (it would be 1/256 fullscale value).

        If you sample on LRCK, you should see those most significant 8 bits change often.

        Thanks,

        Paul

      • 0 in reply to Paul_Frost
        Prodigy 10 points

        Thank you for reply, Mr. Frost.

        The waveform was measured again.
        Since it is a sine wave, the first 8 bits change.

        first half

        second half

        The I2S input waveform is the same for both 24bit-I2S setting and 32bit-I2S settings.
        When invalid data is 0x0000-0000, the output is zero level.(32bit-I2S setting)

        Is there anything I can do to find out the cause?

        Best regard.

      • 0 in reply to Takeo Ootsuka
        TI__Guru 53633 points

        I will try this in the lab when I get a chance, likely today.

      • 0 in reply to Paul_Frost
        Prodigy 10 points

        Thank you, Mr.Frost.

        What was the result of trying it in the lab?
        I look forward to hearing from you.

        Best regerd.

      • +1 in reply to Takeo Ootsuka
        TI__Guru 53633 points

        Hi Ootsuka-san,

        I confirmed that the device works with BCK=128xFS, using 24 bit, left justified data. Unfortunately my resource (AP2722) could not generate 32-bit left justified data, so I have not been able to confirm the exact customer's behavior find a reasonable explanation why one condition works and the other does not. 

        Does the removal of the 0x5555 content in the I2S data line change any of this behavior? That is to say if you make the data line low for those 32 bits, does it still work/not work?

        Thanks,

        Paul

      • 0 in reply to Paul_Frost
        Prodigy 10 points

        Hi Mr frost.
        Thank you for trying.

        The output will stop when changing invalid data from 0x5555 to 0x0000.
        The output will be full range when changing invalid data from 0x5555 to 0x7fff.
        (FMT[2: 0]=100:32bit I2S setting)

        I thought that there might be a problem with the register setting by I2C.
        I changed the design to set the register in SPI.
        However, invalid data is output when FMT [2: 0] = 100.

        The device will be shipped and you will not be able to try it.
        The result is halfway, but it will be closed once.

        Thank you for your support.