DIR9001: DIR9001 and DIT4096 CLK setup

Connie Lu1

Intellectual 2080 points

Part Number: DIR9001
Other Parts Discussed in Thread: DIT4096

Hi team,

My customer have the DIR9001 to receive a SPDIF signal and transmit that data to the DIT4096 via I2S. Then the DIT4096 outputs the SPDIF signal to some external receiver.

What is the best way to connect/setup the CLK setting on the DIT4096 in hardware mode?

If the DIR9001 is the source CLK for the DIT4096 (in this case using the DIR9001 SCKO pin 4), what should the CLK0 and CLK1 settings be for the MCLK on the DIT4096?
- The DIR9001 will be in PLL mode to retrieve the CLK from the SPDIF Input

From the DIT4096 datasheet:

Thanks,

Connie

over 3 years ago

0 Carson Allen over 3 years ago

TI__Genius 13610 points

Hello Connie,

Thanks for your patience I will need to review both datasheets and find optimum configuration for you based on what you detailed. I will reply back within 48 hours.

Best Regards,

Low Power Audio Engineer

0 Carson Allen over 3 years ago

TI__Genius 13610 points

Hello Connie,

What is the sampled rate of the data?

Best Regards,

Carson

0 Austin Smith over 3 years ago

Prodigy 30 points

Hello Carson,

My name is Austin and I am the customer working with Connie on this part.

I believe the sample date rate is variable as the multiple different sources could have different data rates.

0 Carson Allen over 3 years ago in reply to Austin Smith

TI__Genius 13610 points

Hello Austin,

Would those varying sample rates abide by at least one of the three master clock ratios seen in that lower figure?

And what is the MCLK frequency you plan to use?

Carson

0 Austin Smith over 3 years ago in reply to Carson Allen

Prodigy 30 points

Hello Carson,

Yes, the varying Sample Rates would abide by the master clock ratios.

The MCLK would come from the DIR9001 SCKO output. Schematic snippet below:

0 Carson Allen over 3 years ago in reply to Austin Smith

TI__Genius 13610 points

Hello,

By what you have described you would need to just have something controlling the input lines of CLK0 and CLK1 to change setting accordingly with the changing sample rate.

Carson

0 Austin Smith over 3 years ago in reply to Carson Allen

Prodigy 30 points

OK, thank you, good to know.

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DIR9001: DIR9001 and DIT4096 CLK setup