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Hi TI Team,
We want that TLV320ADC3140 configure as 2AMIC+4DMIC, where 2AMIC map to TDM's channel1 and channel 2, and 4DMIC map to TDM's channel 3 to channel 6.
But I used below command fs=48Khz, channels=8 and width=32bits to record audio at CPU end (AM5718, Linux), found that channel 5 and channel 6 in output file 'test.wav' have no data.
root@am57xx-evm:~# arecord -Dhw:0,0 -c 8 -r 48000 -f S32_LE -d 10 test.wav
We guess there may be a problem with the ADC's registers configuration,
Could you help to review it?
Here are some our information for your reference:
1. schematic:
(1) 2 AMICS Placed on INP1 and INP2 for Single ended MICS.
(2) 2 DMICS placed on INP3,INN3 and other 2 DMICS placed on INP4,INN4.
2. ADC's registers setting:
(1) GPI1 & GPI2 are disabled, GPI3 is configured as a PDM data input for channel 3 and channel 4 (PDMDIN2), GPI4 is configured as a PDM data input for channel 5 and channel 6 (PDMDIN3)
(2) GPO1 & GPO2 are disabled, Hi-Z output; GPO3 & GPO4 are configured as a PDM clock output (PDMCLK), Drive active low and active high.
3. waveform of BCLK, FSYNC and SDOUT:
the waveform shows data(SDOUT)'s channel 5 and channel6 have no data.
Thanks.
Best Regards,
Xing-Qin
Hello Xing-Qin,
I will review register dump and respond within 48 hours.
Best Regards,
Carson
Hi Carson,
Thanks for your reply.
I would like to add that the TLV320ADC3140 acts as master, external OSC 24.576MHz input to GPIO pin used as MCLK. BCLK to FSYNC frequency ratio configured to 256, and MCLK to FSYNC ratio configured to 512.
I also configured the HW & SW of TLV320ADC3140 as 8DMICs, and all of 8 channels are normal when recording audio.
Best Regards,
Xing-Qin
Hello Xing-Qin,
There have been delays in handling this issue
Thanks for additional info, I will respond by end of week.
Best,
Carson
Hello Xing,
Im confused to to what GPIO the MCLK is being inputted at?
Best Regards,
Carson
Hi Carson,
Sorry, It is GPIO1 of TLV320ADC3140, the GPIO1 is connected to an external OSC(24.576MHz) and is configured as a master clock input (MCLK).
Thanks,
Best Regards,
Hello
Okay thanks for the info, could you tell me if the data is sharing bus with anything else?
Nothing is obviously wrong here.
You verify inputs are getting data for those channels?
I might need to replicate on bench.
Bes T Regards,
Carson
Hi Carson,
Sorry for my reply so late, and thanks for your reminder.
The data is not share bus with anything else.
We are verifying that the inputs are mapped to corresponding channels or not, and update the result here later.
Thanks,
Best Regards,
Try changing register 0x07 to 0x30 instead of 31 and see if it causes output change.
Hi Carson,
I modified register 0x07 to 0x30, channels 5 and 6 still have no data output.
I want to tell you that we have selected another solution to avoid this issue, the solution is that one ADC used for 4xAMIC and the other one used for 8xDMIC.
So we will not continue to solve this problem,.
Thanks for your supports,
Best Regards,