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DIR9001: AES/EBU input circuit/loop through to next device

Genius 14759 points
Part Number: DIR9001
Other Parts Discussed in Thread: SRC4382, SRC4192, SRC4190

Hi Experts,

Good day and allow me to post this case from client.

Customer is in the development process of a beamforming speaker for professional audio applications. Asking reference guide as follows:

"We need an AES/EBU input (XLR - 3 pin). Therefore we are searching for an interface chip to mange the AES/EBU to I2S conversion. We found the DIR9001 to fit in our needs. But I didn't find any input circuit recommendation for AES/EBU input. Can you send me an example schematic for that use case?

Also we need to daisy-chain the AES/EBU inputs of our device. Therefore we need to loop-through the signal to the next instance. Is it possible to hard connect the input connector pins with the output connector pins (XLR --> XLR)? Or is that problematic due to termination issues?"

Thank you for your support.

Regards,
Archie A.

  • Hi, I found a reference design with DIR9001  in this link:  https://www.ti.com/tool/TIDA-00089. It should provide you with some insightto get started

    Regarding your question, although I am not sure about the application you have in mind , I do not see any issue with XLR==>XLR connection . Should be okay to do daisy chain.

    Regards,

    Arash

  • Hello Arash,

    Thanks for the info and sorry for updating this post late as I have just received new feedback from client.

    Do we also have a layout example for using AES/EBU (symmetrical data transfer)? I couldn't find it elsewhere.

    Thank you.

    Regards,
    Archie A.

  • Sorry Archie, I don't have any layout example for using AES/EBU myself.

    Regards,

    Arash

  • Hello Arash,

    Can you help us recommend chip for AES/EBU?

    We found the SRC4382, it is described with AES/EBU functionality. Further information as per report, customer needs an AES/EBU through-connector on their device, they need to know the latency when the signal is routed directly from DIR to DIT.

    Thank you.

    Regards,
    Archie A.

  • Hello Archi, Beside SRC3483 that you mentioned we have several "sample rate converters" that you can offer such as SRC4190 and SRC4192.

    Regarding the latency of signals I am  quoting from the data sheet :

    The group delay of the SRC interpolation function can be programmed to one of four settings. The actual length of the interpolation filter is unaltered, but the number of samples pre-buffered in the FIFO prior to the re-sampler function can be set to 64, 32, 16, or 8. The FIFO length directly impacts the latency and group delay. By default, the number of samples pre-buffered is set to 64. The decimation filter includes a direct down-sampling option. This option should only be used in cases where the output sampling rate is higher than the input sampling rate. The advantage of using the direct down-sampling option is that it results in zero latency operation, as it simply selects one out of every 16 samples from the resampler output without applying low-pass anti-aliasing filtering. By contrast, the decimation filter response adds 36.46875 samples of group delay. 

    I hope that answers their question. 

    Regards,

    Arash