TLV320DAC3203EVM-K: PLL powered on while not needed?

gustavo zarba

Part Number: TLV320DAC3203EVM-K
Other Parts Discussed in Thread: TLV320DAC3203

Hi Ivan,

going on with the settings of the TLV320DAC3203, I am now testing with a higher MCLK.

I read in the Reference Guide (slau434a), by the settings for Fast Startup:
"The system used to develop this configuration has a MCLK input of 12.288-MHz, the device is configured as slave for the I2S interface and the sampling frequency is 48-kHz. So the device would only need to divide MCLK by 256 to obtain the desired sampling frequency, thus there is no need to power up and configure the PLL. As a side note, keep in mind that it is always recommended to set DOSR to 128 for best audio quality"

So, actually, the PLL is not being used by this MCLK frequency.
Since I cannot find how to change the frequency of MCLK in the EVAL Kit, I decided to try with the standard frequency of 11.296-MHz

With this MCLK being divided by 256, we get 44.1 kHz Sampling frequency. Here too, the PLL should not be needed.
However, the EVM powers the PLL on.(Digital Microphone Loopback Script)

If I deactivate the PLL, the Mics are not geting any clock.

Any reason for this? What should I change in the script to avoid using the PLL (and save on energy consumption)?

Best regards from Germany!
Gustavo

9 months ago

0 Ivan Salazar 9 months ago

TI__Guru* 98235 points

Hi Gustavo,

The PDMCK is derived from the output of MADC, or MDAC if MADC is not enabled. What is the NDAC and MDAC value on your configuration?

You could share the script you're using, then we can compare that with the settings required for digital mic configuration.

Best regards,
-Ivan Salazar
Applications Engineer

0 gustavo zarba 9 months ago in reply to Ivan Salazar

Expert 1110 points

Hi Ivan,

here is the configuration. It is derived from the Digital Microphone Loopback Script.
Something is strange for me: the script is writing to some reserved registers ( 0x12 and 0x13) to set:
    # NADC = 2, MADC = 16, dividers powered on
    w 30 12 82
    w 30 13 90

With this, the ADC dividers are being used, while I do not really need ithe ADC. I guess, otherwise the digital mics get no clock?The panel "ADC Channel Configuration" shows for the Digital Mucrophone the "Digital Mic Input Pin" = SCLK
and for "Digital Mic Routing" = Both ADCs
If I change this to "Disabled" I get no signal from the mics.

Also I set AOSR = 128 w 30 14 80
But the panel shows it as 64. Even after refreshing the panel

And last, I get pop sounds, not regular but loud, like a connection would be bad. It could be a hardware issue extern to the EVAL but I cannot find anything alike. Please, while you check the script, tell me if there is some settinging I can use to stop this.

################################################################################

    # Select Page 0
    w 30 00 00
    # Initialize the device through software reset
    w 30 01 01
    # Select Page 0
    w 30 00 00
    # PLL_clkin = MCLK, codec_clkin = PLL_CLK,
    # PLL on, P=1, R=1, J=8, D=0000
    # Clock Setting Register 1, Multiplexers - 0x00 / 0x04 Value= 11: PLL Clock is CODEC_CLKIN
    w 30 04 03
   #
# This does not work (PLL powered down)
   # Clock Setting Register 2, PLL P&R Values - 0x00 / 0x05 Value= 00010001 = 11
   # D7 =    0:        PLL is powered down
   # D6-D4 =   001:   Reset values
   # D3-D0 =   0001:   Reset values
#    w 30 05 11
    #
# This works (PLL powered up)
   # Clock Setting Register 2, PLL P&R Values - 0x00 / 0x05 Value= 10010001 = 91
   # D7 =    1:        PLL is powered up
   # D6-D4 =   001:   Reset values
   # D3-D0 =   0001:   Reset values
    w 30 05 91
    #
    # Clock Setting Register 3, PLL J Values - 0x00 / 0x06
    # 0x04 reset value
#    w 30 06 04
#
    # Clock Setting Register 3, PLL J Values - 0x00 / 0x06
    w 30 06 08
    #
    # Clock Setting Register 4, PLL D Values (MSB) - 0x00 / 0x07
    w 30 07 00
    # Clock Setting Register 5, PLL D Values (LSB) - 0x00 / 0x08
    w 30 08 00
#
    # Clock Setting Register 6, NDAC Values - 0x00 / 0x0B
    # NDAC = 1, divider powered on
    w 30 0b 82
    # Clock Setting Register 7, MDAC Values - 0x00 / 0x0C
    # MDAC = 2, divider powered on
    w 30 0c 88
    # DOSR = 128
    w 30 0d 00
    w 30 0e 80
#
# Registers 0x12 and 0x13 are reserved
# Why the EVM writes to them ?
    # NADC = 2, MADC = 16, dividers powered on
    w 30 12 82
    w 30 13 90
#
    # AOSR = 64
#    w 30 14 40
#
    # AOSR = 128
    w 30 14 80
#
    # Configure Power Supplies
    w 30 00 01
    # Disable weak AVDD in presence of external AVDD supply
    w 30 01 08
    # Enable Master Analog Power Control
    w 30 02 00
#
   # Analog Input Quick Charging Configuration Register - 0x01 / 0x47
   w 30 47 32
#
   #
    # Set the REF charging time to 40ms
    w 30 7b 01
#
###############################################
# Configure Processing Blocks
###############################################
    # Select Page 0
    w 30 00 00
    # PRB_P2 and PRB_R2 selected
    w 30 3C 02
    w 30 3D 02
#
################################################
# High-pass first order Butterworth2 filter,
# fc = 80 Hz
###############################################
    # Write to Buffer A:
#
    # BIQUAD A, Left Channel (Page 8, Register 36, C7-C11)
    w 30 00 08
# 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
    w 30 24 7E
    w 30 25 F8
    w 30 26 EB
    w 30 27 00
    w 30 28 81
    w 30 29 07
    w 30 2A 15
    w 30 2B 00
    w 30 2C 7E
    w 30 2D F8
    w 30 2E EB
    w 30 2F 00
    w 30 30 7E
    w 30 31 F7
    w 30 32 DD
    w 30 33 00
    w 30 34 82
    w 30 35 0C
    w 30 36 0C
    w 30 37 00
#
    # BIQUAD A, Right Channel (Page 9, Register 44, C39-C43)
    w 30 00 09
# 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
    w 30 2c 7E
    w 30 25 F8
    w 30 26 EB
    w 30 27 00
    w 30 28 81
    w 30 29 07
    w 30 2A 15
    w 30 2B 00
    w 30 2C 7E
    w 30 2D F8
    w 30 2E EB
    w 30 2F 00
    w 30 30 7E
    w 30 31 F7
    w 30 32 DD
    w 30 33 00
    w 30 34 82
    w 30 35 0C
    w 30 36 0C
    w 30 37 00
#
    # Write to Buffer B:
#
    # BIQUAD A, Left Channel (Page 26, Register 36, C7-C11)
    w 30 00 1A
# 24 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
    w 30 24 7E
    w 30 25 F8
    w 30 26 EB
    w 30 27 00
    w 30 28 81
    w 30 29 07
    w 30 2A 15
    w 30 2B 00
    w 30 2C 7E
    w 30 2D F8
    w 30 2E EB
    w 30 2F 00
    w 30 30 7E
    w 30 31 F7
    w 30 32 DD
    w 30 33 00
    w 30 34 82
    w 30 35 0C
    w 30 36 0C
    w 30 37 00
#
    # BIQUAD A, Right Channel (Page 27, Register 44, C39-C43)
    w 30 00 1B
# 2c 7E F8 EB 00 81 07 15 00 7E F8 EB 00 7E F7 DD 00 82 0C 0C 00
    w 30 2c 7E
    w 30 25 F8
    w 30 26 EB
    w 30 27 00
    w 30 28 81
    w 30 29 07
    w 30 2A 15
    w 30 2B 00
    w 30 2C 7E
    w 30 2D F8
    w 30 2E EB
    w 30 2F 00
    w 30 30 7E
    w 30 31 F7
    w 30 32 DD
    w 30 33 00
    w 30 34 82
    w 30 35 0C
    w 30 36 0C
    w 30 37 00
#
###############################################
# Configure ADC Channel
###############################################
    # Select Page 0
    w 30 00 00
    # Configure MISO as clock output for DIGMIC
    w 30 37 0E
    # LADC and RADC enabled for DIGMIC
    # Route SCLK as DIGMIC_DATA
    # Power up LADC/RADC
    w 30 51 DC
    # Unmute LADC/RADC
    w 30 52 00
#
###############################################
# Configure DAC Channel with Soft Stepping
###############################################
#
    # Select Page 1
    w 30 00 01
    # Set HP power up time for NO POP
#    w 30 14 29
    w 30 14 25
    # Route LDAC/RDAC to HPL/HPR
   w 30 0c 08
   w 30 0d 08
   #
    # Select Page 0
    w 30 00 00
    # DAC => 0dB
    w 30 41 00
    w 30 42 00
    # Power up LDAC/RDAC
    w 30 3f d6
    #
    # Select Page 1
    w 30 00 01
    # Unmute HPL/HPR driver, 0dB Gain
    w 30 10 00
    w 30 11 00
    # Power up HPL/HPR
    w 30 09 30
#
#
###############################################
    # Wait for 2.5 sec for soft stepping to take effect
    d 3
    # else read page 1, register 63d, D(7:6). When = “11” soft-stepping is complete
###############################################
#
    # Select Page 0
    w 30 00 00
    # Unmute LDAC/RDAC
    w 30 40 00
#
###############################################

Best regards,
Gustavo

0 Ivan Salazar 9 months ago in reply to gustavo zarba

TI__Guru* 98235 points

Hi Gustavo.

Adding a few notes below:

This may just be missing but register 0x04 configuration must change if not using the PLL. Bits 1-0 must be 0 to route MCLK directly to CODEC_CLKIN. A value of 3 on this register would mean BCLK routed to PLL, then PLL to CODEC_CLKIN
The diagrams in data sheet and GUI may not be very clear, but DIG_MIC_CLK (or PDMCK) is output from MADC divider, thus if this part of the dividers is disabled, then DIG_MIC_CLK will be disabled as well.
What is the PDMCK frequency you need for the digital mics? Is it 3.072MHz?
If using MCLK instead of BCLK, and no PLL, the other dividers would change as well. You could try with these values:
- NDAC=1, MDAC=2, DOSR=128
- NADC=2, MADC=2, AOSR=64 (these values are different than DAC in order to make DIG_MIC_CLK = 3.072MHz)

Hope this helps getting the correct device configuration/ Let me know if there are any questions.

Best regards,
-Ivan Salazar
Applications Engineer

0 gustavo zarba 9 months ago in reply to Ivan Salazar

Expert 1110 points

Hi Ivan, thanks for your patience!

Now the question about having the dividers for the ADC part working is clear.
And so the way of not using the PLL for the CODEC_CLKIN.
And also AOSR=64 is clear
But...

Question 1:
the GUI does not show the value of DIG_MIC_CLK (or I cannot find it)
However, the User Guide for the TLV320DAC3203 says:

DIG_MIC_CLK = CODEC_CLKIN / NADC x MADC

How do I come to the DIG_MIC_CLK = 3.072MHz ?
Because there is no way to find any non-fractional Value for NADC and MADC to do this math...

Actually, this arises the second question:

The mics can accept any Clock value between 1.000 and 4.800 MHz
Since I am not using the data coming from the mics outside of the DAC (I need the processing blocks, filters, etc, but everything goes to the HPs),
should I care about?

If the DIG_MIC_CLK is a relative value handled intern by the DAC and my mics can handle it, is fine for me.

I appreciate your help a lot, thanks!

Best regards,

Gustavo

+1 Ivan Salazar 9 months ago in reply to gustavo zarba

TI__Guru* 98235 points

Hi Gustavo,

If we assume MCLK = 12.288MHz, and don't use the PLL along with the suggested divider values, the result would be DIG_MIC_CLK = 12.288MHz / (2 * 2) = 3.072MHz. I think this is the MCLK on your system but let me know otherwise.

The clock used for the digital mics is pretty much the sampling frequency, which is then decimated by the ADC down to Fs = 48kHz in this case. This is pretty much the ratio of AOSR so as long as it matches to DIG_MIC_CLK vs ADC_Fs it should be OK. 3.072MHz is a common PDMCK frequency for 48kHz ADC sampling rate.

Best regards,
-Ivan Salazar
Applications Engineer

0 gustavo zarba 9 months ago in reply to Ivan Salazar

Expert 1110 points

Hi Ivan,

My apologies for the confusion. I started by using a rater low MCLK frequency of 2.048MHz, because I was aiming to save energy by the MCU, but then I changed my mind and went for the 12.288MHz and 48kHz without PLL, which should be more effective to save energy, since the MCU only works for the configuration of the audio chip.

However, since I cannot set the 12.288MHz as MCLK on the EVM, and because I want to be sure my comands work before I go into the final testing of my own hardware, I am now working with the 11.2896MHz the EVM provides. And with this, I get 2.8224 as PDMCK.

We were talking about two different MCLK frequencys, that is why I could not find out how you get to the 3.072MHz!

I am now traveling again and cannot check this all, but next week I will do it and get back here to share the results.

Thank you very much for the quick reactions to my questions.

Best regards, this time from France!
Gustavo

0 Ivan Salazar 9 months ago in reply to gustavo zarba

TI__Guru* 98235 points

Hi Gustavo,

Understood, thanks clarifying that. Let us know how the test goes once you're back and if you need any further assistance.

Best regards,
-Ivan Salazar
Applications Engineer

0 gustavo zarba 8 months ago in reply to Ivan Salazar

Expert 1110 points

Hi Ivan!
I succeeded with the tests on the EVM, thanks for all the tips!

Like it had to be, I destroyed the analog part of the chip by testing with my board.
My error, I tested it with 3.3V while it was expecting 1.8V...

U have some questions around this subject, but I will open another thread for this.

So, we can close this one, thanks again!
Gustavo

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TLV320DAC3203EVM-K: PLL powered on while not needed?