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Original question:

Can MCLK of the TLV320AIC3200 stop during the operation?

TLV320AIC3120: Register settings for TLV320AIC3120

Ashlin Surey
Prodigy 20 points
Part Number: TLV320AIC3120

Hi,

We are trying to interface the TLV320AIC3120 audio codec with the Qualcomm QCS610 chipset. We are using the /sound/soc/codecs/tlv320aic31xx.c driver file. We are facing some issues in the Qualcomm platform that after writting the default settings we are not observing any activity in the I2C bus when using the snd_soc_write, snd_soc_read and snd_soc_update_bits function calls.

We are working in S16_LE, 48KHz Sampling rate, Stereo speaker. The processor will generate 12.288MHz MCLK. 

We would like to properly configure the audio codec chip (programing the divider values, unmute the device and enabling the playback and capture switches etx) in the default settings itself by enabling the SPK output and MIC input in the default settings. Can you provide us the register settings to configure the codec in the i2c_probe function itself?


  • 0
    TI__Genius 9730 points

    Kindly apply for the codec_control tool, it will help you to generate the register setting.I will transfer your request to our codec expert.

  • 0 in reply to Shenghao Ding
    TI__Mastermind 29745 points

    Hi,

    You can use the PLL calculator to configure the PLL divider in this product folder.

    TLV320AIC3120 data sheet, product information and support | TI.com

    Also, in the datasheet, there are some examples to configure the device either for record (7.3.11) or playback (7.3.12.15). 

    I have created a script for MIC1LP and SPK output based on your statement above. This is not a loopback path, but an independent record and playback path. You can configure or modify as needed per your requirements. Also, this is in slave mode with 16-bit word length and 48KHz sampling.

    setting with SPK and MIC1LP.txt 
    #			--------------------------------------------------------------- page 0 is selected 
w 30 00 00
#			 s/w reset
w 30 00 01
#			 PLL_clkin = MCLK=12.288MHz, Fs=48KHz ,codec_clkin = PLL_CLK
w 30 04 03
#			 PLL Power up, P = 1, R = 1
w 30 05 91
#			 J = 8
w 30 06 08
#			 D = 0000, D(13:8) = 0
w 30 07 00
#			 D(7:0) = 0
w 30 08 00
#			 NDAC is powered up and set to 4
w 30 0b 84
#			 MDAC is powered up and set to 4
w 30 0c 84
#			 DOSR = 128, DOSR(9:8) = 0
w 30 0d 00
#			 DOSR(7:0) = 128
w 30 0e 80
#			 NADC is powered up and set to 4
w 30 12 84
#			 MADC is powered up and set to 4
w 30 13 84
#			 AOSR(7:0) = 128
w 30 14 80
#			 mode is i2s, wordlength is 16 in slave mode
w 30 1b 00
# 			 PRB_P16
w 30 3C 10
# 			 PRB_R4
w 30 3d 04
#			--------------------------------------------------------------- page 8 is selected
w 30 00 08
# 			 Enable Adaptive Filtering in DAC
w 30 01 04
#			--------------------------------------------------------------- page 1 is selected
w 30 00 01
#			 DAC routed to SPK
w 30 23 40
#			 Unmute Class-D, set gain = 18 dB
w 30 2a 14
#			 Power-up Class-D drivers
w 30 20 86
# 			 Enable Class-D output analog volume, set = -9 dB
w 30 26 92
#			 MIC BIAS = AVDD
w 30 2e 0b
#			 MICPGA P = MIC1LP 20kohm
w 30 30 80
#			 MICPGA M - CM 20kohm
w 30 31 80
#			--------------------------------------------------------------- page 0 is selected
w 30 00 00
#			 POWERUP ADC channel
w 30 51 80
#			 UNMUTE ADC channel
w 30 52 00
#			 POWERUP DAC, data path = left and right channels [(L + R) / 2] 
w 30 3f b0
#			 DAC volume 0dB
w 30 41 00
#			 UNMUTE DAC 
w 30 40 04

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 20 points

    Thank you so much for the details. I'll test with this setting.

  • 0 in reply to pdjuandi
    Prodigy 20 points

    Hi,

    Can you provide the settings for using a digital microphone in TLV320aic3120 in the GPIO1 and DIN pins?

    Thanks.

  • 0 in reply to Ashlin Surey
    TI__Expert 6620 points

    Hello,

    Peter is currently out of office. He will return on Monday and will get back to you then. Thank you for your patience!

    Regards,
    Sydney Northcutt 

  • 0 in reply to Ashlin Surey
    TI__Mastermind 29745 points

    You can refer to page 0 register 51 bits D5-D2 (1010) for configuring the DMIC clock to GPIO1. DIN for DMIC is configured on Page 0 Register 81 bits D5-D4 (10).

  • 0 in reply to pdjuandi
    Prodigy 20 points

    Thanks for the details. We have one more clarification on this.

    If we use Digital MIC through the pins of DIN & GPIO1(Clk), How do send the Audio data to Speaker Over I2S line from Processor?

  • 0 in reply to Ashlin Surey
    TI__Mastermind 29745 points

    DMIC is for recording and what you are asking is playing data from processor to speaker output. These are 2 different paths.

    If you are thinking of sending the data from the DMIC to speaker, then there's a register in Page 0 Register 29 for ADC-DAC loopback. 

    Regards.

  • 0 in reply to pdjuandi
    Prodigy 20 points

    We are interfacing the codec with the processor through I2S. If we connect the DIN pin with the DMIC, how can we connect the DIN and DOUT for I2S interface with the processor? As we will need the DIN pin to send the audio data from processor to the codec through I2S for playback.

  • 0 in reply to Ashlin Surey
    TI__Mastermind 29745 points

    Are you running both concurrently, meaning recording and playback? The bits or registers are configurable, so you can change it back to DIN for I2S when you are done with recording. 

  • 0 in reply to pdjuandi
    Prodigy 20 points

    Yes, as per our use case, we will recording and playback simultaneously. Is this supported in this codec? If not, can u suggest any other codec with this support.

  • 0 in reply to Ashlin Surey
    TI__Mastermind 29745 points

    You can look at this high-level summary for some of the devices. AIC3106 DMIC is on GPIO1 and GPIO2 for example which you can use but check against your requirement from the list.

    7317.AIC products.pdf