TAS5720A-Q1: Clock error ? Unable to get audio.

Hi Jarul,

As you probably are aware the CLKE error usually indicates that MCLK, LRCK, and/or SCLK are either:
1. Non-supported ratio
2. Non-supported rate
3. One of the clocks has stopped

I noticed that your MCLK is about 62kHz off from what it should be if you are calculating it through MCLK = 256*48k = 12.288MHz.

If possible I would recommend running that at 12.288MHz and seeing if you start getting the correct output.

The SCLK is 4kHz off as well, so I'd recommend changing that to be 1.536MHz.


Best Regards,

Robert Clifton

Hello Robert,

When checked theoretically, the MCLK and SCLK are received as 256Fs and 32FS respectively. However when measuring the same using DSO, the reading for MCLK is 12.35 MHz and for SCLK it is 1.54 MHz, which is a little over the expected value of 1.536 MHz, I suspect that would be due to rounding off to 2 decimal places.

The DIV bits, set in TCR2 is being set as 3, i.e. (((MCLK / SCLK) / 2) - 1), Thus confirming that SAI and TAS5720 both receive MCLK of 12.288 MHz frequency. [originally, the MCLK freq. for SAI was 1024Fs, thus DIV was 7]

As per my understanding of the code, the SPK-SD bit of the Power Control Register, a Control Port Register, gets toggled from High -> Low -> High, when the audio test vector is being played. This toggling happens multiple times, through out the execution of the test vector.

What might be the reason for the 62kHz extra MCLK freq. ? Any suggestion on what might help me to get correct MCLK ?

Thank you.

Hi Jarul,

Let's take a step back here just so I can follow better. What are you using to create and send the MCLK to the TAS5720A-Q1?

Regards,

Robert Clifton

Hello Robert,

Apologies for a late reply. TAS5720A-Q1 is configured to be a slave device. Hence the SAI does the task of generating MCLK. As per my understanding, MCLK gets generated when SAI's probe function is executed. a call to devm_clk_get(&pdev->dev, i) seems to set the 4 probable MCLK values.

On the codec side, the MCLK is set and enabled in its probe function.

I hope this is the information you wished to know.

Thanks,
Jarul Mehta

Hi Jarul,

Do you have any way of making that output a more accurate MCLK frequency?

Regards,

Robert Clifton

Hi Robert,

Following is my observation so far:

• I am able to get all 3 CLKs generated.

• MCLK = 12.228 MHz

• When measuring it practically using a DSO, the value measured fluctuates between 12.25 MHz, 12.29 MHz, 12.32 MHz and 12.35 MHz.

• BCLK = 1.54 MHz (as desired)
• LRCK = 48 KHz (as desired)

• We have verified the CLKs and output for working a WM8960 codec
• Observations:
• MCLK fluctuation is observed.
• The TX register values for SAI are observed to be same for both codecs, WM8960 and TAS5720.
• FSL_SAI_TCSR = 0xD0170C01 [when the audio playing is started, the value of this register is 0, which later changes to this value when audio is terminated]
  FSL_SAI_TCR1 = 0x3A
  FSL_SAI_TCR2 = 0x700000F
  FSL_SAI_TCR3 = 0x10000
  FSL_SAI_TCR4 = 0x10F1B
  FSL_SAI_TCR5 = 0xF0F0F00
• 2 sound cards are registered, each with 2 devices:

**** List of PLAYBACK Hardware Devices ****
card 0: wm8960audio [wm8960-audio], device 0: HiFi wm8960-hifi-0 []        (for WM8960)
card 0: tas5720audio [tas5720-audio], device 0: HiFi tas5720-amplifier-0 []    (for TAS5720)
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 0: wm8960audio [wm8960-audio], device 1: HiFi-ASRC-FE (*) []        (for WM8960)
card 0: tas5720audio [tas5720-audio], device 1: HiFi-ASRC-FE (*) []            (for TAS5720)
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: amixaudiosai [amix-audio-sai], device 0: HiFi-AMIX-FE (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: amixaudiosai [amix-audio-sai], device 1: HiFi-AMIX-FE (*) []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

• Enabled ASRC support for TAS5720 as per WM8960 functionality.

• Over current hardware fault (OCE) is detected when audio playing commences for TAS5720 codec.

• It is observed that when the audio test vector is being played, the CLK ERR bit of 0x08 codec register is low, indicating correct CLK rates and proper availability of the same. This bit later goes high, once the audio playing is terminated.
• The fault configuration and error status register value is read to be 0x04, when the audio test vector is being played, i.e. OCE bit is set high.
• Once the audio test vector terminates, and the shutting down process starts, the register value changes to 0x0C, i.e. CLKE and OCE bits are set high.
• After the control returns from the aplay command, back to the terminal, the register value is found to be 0x08, i.e. only CLKE is set high.
• Reasoning:
• I assume that this variety of register values might be observed as the CLKs are readily available earlier, hence only OCE bit is set (0x04)
• Later, when the audio playback is completed, and the SAI shutdown procedure starts, the CLKE and OCE bits are set high (0x0C). We assume that the CLKs are disabled when SAI is shutdown.
• When the complete procedure of playing an audio is terminated, and the control comes back to terminal, only the CLKE bit is set high (0x08).

• A speaker of 1 W, 8 ohms is connected to be board. When audio is started, a feeble sound of speaker turning ON is heard, but no output audio is audible.

On setting AMP_MUTE (SPK_SLEEP/ADR) = 0 in device platform's probe function, Audio playing is not supported, also I2C registers are not accessible The system returns error in setting SAIF format, and Codec DAI is not being set.