PCM4222: PCM4222 Full scale

Hello!

Good question, it's one we get fairly regularly on differential input ADCs.  In short, each individual ADC input can accept up to 2.8Vpp and because the differential input signal to the ADC is IN+ - IN- you'll have +2.8V when IN+ is at the positive full-scale and IN- is at negative full-scale and you'll get -2.8V when IN- is at positive full-scale while IN+ is at negative full-scale.  Therefore the min/max differential inputs are +2.8V and -2.8V, or 5.6Vpp.  This is explained in the following video:   https://training.ti.com/ti-precision-labs-adcs-sar-adc-input-types?context=1139747-1128375-1139103-1128659 for a more visual explanation.  

With that explained, it's possible that you're experiencing some clipping our output signal swing related limitations out of the OPA1632 circuit depending on the power-supplies you're supplying it with.  Can you confirm the power-supply connections to both the OPA1632 and PCM4222?  A schematic says a thousand words so if you share that we can review other connections as well.  

Also, to be sure of what we think is going on can you submit an oscilloscope capture right at the pins of the PCM4222?

Thank you Steve, thank you Collin

I am truly embarassed that I didn`t know how to measure those 5.6V pp

If you are so kind, please take a look at the PCM4222EVM schematic that I have used with just these 2 modifications:

- R9, R10, R11 and R12 are modified by us to 270R, so that we could double the gain, and 

- R2 and R6 are tied to the ground, so that we can use this circuit as a single ended input

Please confirm if what I have modified it is correct and, given the input buffer circuit now has unity gain, please tell me what should be the pp input voltage requirement at the single ended inputs ( R1 and R5 ) , necessary  for reaching full scale (5.6V pp) on the ADC inputs?

Your answers will end my pain, the never-ending struggle between: "it is a hardware issue" coming from the IT department and "it is a software issue" coming from the hardware department  

Again, thank you very much for your time

Hi

Any update on this??

Hi Michael,

Can you send some oscilloscope captures right at the inputs of the PCM4222 this will help us better see what's going into the ADC?  Also, can you confirm that you're powering the OPA1632 from +/-15V?

With the schematicwe sent above and taking into consideration the changes we made, can you?
1. confirm that what we have modified is correct and if so,
2. given that the input buffer circuit now has unity gain, what should be the pp input voltage required at the single ended inputs ( R1 and R5 ) , to be able to reach full scale (5.6V pp) on the ADC inputs?
Michael

Regarding  oscilloscope , we will send ASAP

Regarding  +/-15V we confirm we are powering the OPA1632 from +/-15V

Thank you so much Collin 

It was very helpful, thank you so much. Meanwhile, I have studied this document,

it  became obvious that I needed to do it.

I have prepared a decent signal generator and I will post the readings after I finish fine tuning the gain values.

If you are so kind to continue helping me, tthere is one more thing that will help me further improve my hardware. 

Now, that we have estabilished that the schematic is correct, given that the + 14.2 V and - 14.2 V rails are supplied by a TPS65131 followed by very high quality LDO s,  TPS7A4701 and TPS7A3301 and the 4 V VCC is supplied trough a ultra low noise LDO , only 0.8μVRMS rms noise and 79dB PSRR, a tidy multilayer pcb layout where we took good care of the audio specific design rules and Texas Instruments recomandations, a clock source that has a typical 140 fS rms jitter,  an fpga for I2S processing, we expect to be able to benefit of the very high quality of the best ADC available, the PCM4222.

Still, a recorded file with no input signal (the single ended input tied to GND) shows in Audacity a noise floor level at around -100dB.

Could you please help me, if you repeat such an experiment on a PCM4222EVM, no signal on the input, what is the noise floor level that you can see on Audacity ? If your result will be better than mine, as I expect, it will mean that I will have to continue searching for the cause of my poor results.

Hello,

The sine wave in your image looks really noisy and on a 1V/div scale you have >250mVpp of noise which seems really high.  You may want to check your grounds and other connections to make sure things are okay.  

We can get into the lab to help with some PCM4222EVM measurements but it will likely take us until Wednesday next week due to other pending lab work.  Thank you for your patience.

Chris, 

What is the interface you are using to connect the PCM4222 to Audacity?  

best regards,

-Steve Wilson

Hi Steve!

I use an FPGA customized by XMOS, that is a  I2S to USB Audio Class 2.0 and a really serious clock source

I was hoping that you might have a s/pdif interface, or anything that would allow you to interface the PCM4222EVM to a computer, as I can only rest when I can match the performance that you can obtain from the dev board

That is the beauty when it comes to testing a audio ADC performance, it is really easy to check and visualize the digitized signal using Audacity. The opposite, testing real life performance of a DAC requires a really expensive setup

The noise floor level that I obtained from my implementation of the PCM4222 and another issue (DIX4192) are still torturing me, but, once I fix them ... 

Thank you for your help!

Best regards

Chris, 

That sounds great.  Is the FPGA providing MCLK to the PCM4222 as well?  if so are you connecting it to J11? 

It sounds like you are running the PCM4222 as a I2S slave, is that right? 

best regards,

-Steve Wilson

Hi Steve!

Yes, the FPGA is providing the MCLK to the PCM4222 that ooerates in slave mode.

Do you have any means of capturing and converting the I2S output of the PCM4222 into an audio file that could be used on a computer ? If yes, such a file, genereted while no signal being applied at the inputs of the complete circuit, including the OPA1632, would offer an accurate representation of what I shoud expect from my implementation in respect to the noise floor

Thank you !

Best regards

Christian, 

Just wanted to ensure your setup was good.  The EVM should of course give you much better performance than you are seeing. We could demonstrate the performance on the AP,  but we can also demonstrate by using jumpers to our new XMOS based EVM motherboard to get a real apples to apples comparison.

As Collin mentioned, we are a little backed up with lab requests.  but we should be able to demonstrate this Wednesday or so. 

best regards,

-Steve Wilson

Hi Steve!

I can`t find any documentation related to this new XMOS dev board.

Could you please PM me the documentation of it? It would be truly useful to me!

Thank you so much

Best regards

Hi Steve, Hi Collin

Found my mistake and cured it, now the initial issue is sorted, I am getting the right recordings now. The pictures are showing the chopped signal and the correct one, after fixing the mistake.   Thank you both for helping me with this one.

While I was testing, I was eliminating the input stages one by one, to observe what adds unwanted noise.

I ended up short-circuiting VINL+ to VINL- and VINR+ to VINR- (anyway, there was less than 1mV between them, OPA1632 is doing a really good job)

I also tried to connect VINL+ and VINL- to Vocm L … No matter what I tried, the best result was a file that presents noise at -114dB

The dynamic range should be -123dB on I2S, but at -60dB input. Since for me would be much harder to distinguish the noise floor from a signal at -60dB, I will kindly ask you to tell me if your pcb layout, input buffer and power supply choice can create a recording with nothing on the input that presents a lower noise floor, so that I understand if I need to dig deeper to find any mistake, or what I have is good. 

I agree, such a level might disturb a hunting dog, or a bat, as for sure I can`t hear it. I will spare you the “audiophile” descriptions of the “transparency” and the magic effects of who knows what cables :)) Actually, it works and sounds excellent, as I expected. BB/TI. Of course.

If I am not abusing your good will, your expertise might also help me  decide the correct gain. 

I understand that the reference level for pro equipment is 1.228 Vrms at -20dB Fs for USA or at -18dB FS for Europe, I also understand that consumer reference level is 0.316 Vrms, but I can`t find any reference regarding the corresponding Fs for that consumer reference level…  I could only find an ADC made by a major brand that specifies that their analog input generates a -13 dB Fs for a - 7.78 dBu, that being the reference level for consumer, 0.316V rms. Should I do the same ?

Basically, I need to decide what should be a minimum acceptable input level useful for recording a consumer electronic source at close to full scale. I guess, my users might want to record outputs generated by reel-to-reel machines and from a large variety of phono stages 

Thank you so much for your help!

Best regards

Hello again!

While we are waiting for the results obtained by you, as a reference, and for that information, we brought a current probe thst might give us a hint in finding the noise source. Still, the results obtained by you will be our reference

Thank you!

Best regards

Chris, 

We ended up just using an AP27xx audio analyzer rather than audacity.   but here is our FFT from the EVM with a 997hz -60dB input.  Apologies for the image quality and color scheme,  I forgot to set the background color to white before saving the image and the red line is a little hard to see. 

best regards,

-Steve Wilson

Hi Steve, hi Collin!

I want to thank you both for your help.

After extensive testing and tuning, we have managed to achieve something beyond our expectations.

Attached, two screenshots made while recording at 24/192 and while reproducing the recorded file

This is exactly why we chose Texas Instruments, extreme high quality components and perfect support !

Best regards