Hi Kato-san,
Are you asking for typical values for the CF and RF components in the highlighted portion of the schematic? If so, really depends on the supply limits of the amplifier. For example, we use 820Ω and 2700pF in the recommended schematic in the PDS.
If you are looking for the output impedance of the PCM itself, that is a bit more difficult to define. Most modern DACs are current segment architectures, so they are essentially a current-source with a pair of switches.
This is a bit harder to model, as you could argue that it has infinite output impedance if it looks like a true current source. I think the best way to think about it is to ask yourself: "what is the output load regulation?" If you measure the current on IOUT, and sweep the voltage on pin, the current ideally would not change. That would mean you have very good output load regulation. Now once the voltage get too high, the system will run out of headroom and the current will start to change, but that should be avoided in the design.
All of this to say, I do not know what the output impedance is that will best suit your model. In regards to the capacitive impedance, at the very least you could put a few (5-10pF) on the output to simulate the parasitic cap load on the pin.
Here is an interesting article, though the output stage is not very relevant: 
Thanks,
Paul
Hi Paul-san,
Thank you for the information.
I would change the way you ask questions.
As you know, NE5534 is used as the I/V converter in PCM1795 data sheet, so how is the phase margin calculated ?
Could you please give me your advice as I would like to simulate it with TINA-TI.
Best regards,
Kato
Hi Kato-san,
I apologize for the delay. Calculating the phase margin for these circuits can be difficult. Generally, I analyze the % overshoot and gain peaking of both amplifier stages together to estimate the phase margin.
Basically, you set the current generator as a small step function. I am using 0.5mA.
You can then look at the overshoot and gain peaking of the simulation and compare the value to curves below:
These can be found in the Analog Engineer's Pocket Reference. https://www.ti.com/seclit/ml/slyw038c/slyw038c.pdf
In this case, I measured about 10% overshoot and about 0.263dB of gain peaking:
You can use the Analog Engineer's Calculator to find the exact point on the overshoot and gain peaking curve: http://www.ti.com/tool/ANALOG-ENGINEER-CALC
For example, I calculated about 57° phase margin for this circuit on the final stage. The first stage had no peaking or overshoot, which indicates greater than 68° margin for the first stage.
You can try the same simulation with different amps and filter designs as well.
Thanks,
Paul
