• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 2 answers
  • Subscribers 32 subscribers
  • Views 1234 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLV320ADC3100: TLV320ADC3100 Linux driver

Yangbo
Intellectual 1690 points
Part Number: TLV320ADC3100
Other Parts Discussed in Thread: TLV320ADC3140

Hi Expert,

My customer is using TLV320ADC3100 under Linux. Here is two questions:

1. Does TI have driver for Linux kernel 4.9 or 4.x? Any related driver could be helpful for them. Please give us the source file. I found a Linux driver for TLV320ADC3140(http://www.ti.com/tool/TLV320ADC5140SW-LINUX). But I can't get the source file. Could you help to download it?

2. They want to know whether it should be enabled with some registers to be initialized or the firmware which is necessary to be needed or not.

Regards,

Yangbo

  • 0
    TI__Guru 63185 points

    Hi Yangbo,

    I'll connect with you directly via e-mail on this.

    1.) Yes, we just need to update the link to point to the correct repository.

    2.) Yes, they'll have to configure the ADC3100 on power-up because it does not have the non-volatile memory required to boot-up from previous configurations.

  • 0 in reply to Collin Wells
    Prodigy 30 points

    Hi, Collin:

    I2S configuration：

    Sample Rate: 48KHZ
    MCLK: 9.6MHZ
    Word Length: 16

    Registers cofiguration are:

    00:00 // change to page 0
    01:01 // reset all registers
    04:00 // PLL_CLKIN = MCLK, CODEC_CLKIN = MCLK
    05:11 // PLL is powered down, PLL divider P = 1, PLL multiplier R = 1
    06:04 // PLL multiplier J = 4 (default)
    07:00 // PLL D-VAL MSB is set to 0
    08:00 // PLL D-VAL LSB is set to 0
    05:11 // PLL is powered down, PLL divider P = 1, PLL multiplier R = 1
    12:81 // NADC clock divider is powered up, NADC clock divider = 1
    13:82 // ADC MADC clock divider is powered up, MADC clock divider = 2
    14:64 // AOSR = 100
    1B:00 // ADC interface = I2S, ADC interface word length = 16 bits, BCLK is input, WCLK is input, Tri-stating of DOUT: disabled
    3D:01 // Select ADC signal processing block PRB_R1
    56:80 // Left AGC enabled, 000: Left AGC target level = –5.5 dB
    00:01 // change to page 1
    33:60 // MICBIAS1 is connected to AVDD
    3B:00 // Left PGA is not muted,  Left PGA gain = 0 dB
    3C:00 // Right PGA is not muted, Right PGA gain = 0 dB
    34:FC // Is not connected to the left ADC PGA, Is not connected to the left ADC PGA, Is not connected to the left ADC PGA
    37:FC // Not connected to the right ADC PGA, Not connected to the right ADC PGA, Not connected to the right ADC PGA
    00:00 // change to page 0
    51:C2 // Left-channel ADC is powered up, Right-channel ADC is powered up, ADC channel volume control soft-stepping is enabled for one step / 2 fS
    52:00 // Left ADC channel not muted, Left ADC channel fine gain = 0 dB, Right ADC channel not muted, Right ADC channel fine gain = 0 dB

    Bellow is our hardware design. Actually, I just connect microphone to MIC2 during record. But the captured volume is very low. Help me check wether registers cofiguration is right?

  • 0
    TI__Expert 6995 points

    Yangbo,

    Here is the link for the TLV320ADCx140 linux driver.

    The device tree binding example is at:

    The documentation with the example at the end of the document to setup the I2C is at: 

    By the way, this driver is meant to run with Linux v5.x. The Linux ALSA drivers changed somewhere around v4.x and these drivers are not compatible with earlier versions.

    Note that the TLV320ADCx140 number of channels, features, and device register set is different than TLV320ADC3100. The overall structure of the linux driver is similar, but you will have to replace all the register commands from the TLV320ADCx140 with the corresponding commands of the TLV320ADC3100. Also the startup is different for both devices and needs to be replaced. For instance, TLV320ADCx140 has an auto-configuration for the PLL clock that is not present on TLV320ADC3100 and the PLL needs to be configured after reset.

    Also note that the output of most microphones has a very low signal swing. Use the PGA to boost this signal to be a little under the maximum input signal swing of the TLV320ADC3100.

    Best regards,
    Pedro

  • 0 in reply to PedroGelabert
    Prodigy 30 points

    hi  

    Registers cofiguration：

    {0x00, 0x00}, {0x01, 0x01}, {0x04, 0x03}, {0x05, 0xDC},
    {0x06, 0x04}, {0x07, 0x00}, {0x08, 0x00}, {0x12, 0x83},
    {0x13, 0x85}, {0x14, 0x80}, {0x1D, 0x02}, {0x1E, 0x84},
    {0x1B, 0x00}, {0x00, 0x01}, {0x33, 0x60}, {0x3B, 0x32},
    {0x32, 0x00}, {0x34, 0xFC}, {0x37, 0xFC}, {0x00, 0x00},
    {0x51, 0xC2}, {0x52, 0x00}, {0x53, 0x28}, {0x54, 0x28},Click here to play this audio clip
    {0x3D, 0x01}, {0x56, 0x80}, {0x5E, 0x80},

    the codec can recorded sound，but the sound is too low，pls checkout our register config，

    thanks

  • 0 in reply to cary he
    TI__Mastermind 22950 points

    Hello Yangbo,

    Is the most recent configuration correct? If so, find my comments/questions below:

    1. Is BCLK intended to be an input? In Page 0, Register 30, the BCLK divider is on and a value is selected. This should be off if BCLK is an input. 

    2. Page 1, Register 50, is getting written a value of 00. This should not be written as this is a reserved register. 

    3. Is the current configuration supposed to be IN2L(P), IN3L(M) --> LADC? If so, please write 0x3F to Register 52, Page 1. 

    Please let me know if this helps.

    Regards,

    Aaron

  • 0 in reply to Aaron Estrada
    Prodigy 30 points

    hi 

    thanks for you great support

    the codec can record sound of LADC and sound volume is okay,but the RADC is also low,

    {0x00, 0x00}, {0x01, 0x01}, {0x04, 0x03}, {0x05, 0xDC},
    {0x06, 0x04}, {0x07, 0x00}, {0x08, 0x00}, {0x12, 0x83},
    {0x13, 0x85}, {0x14, 0x80}, {0x1D, 0x02}, {0x1E, 0x00}, 
    {0x1B, 0x00}, {0x00, 0x01}, {0x33, 0x60}, {0x3B, 0x32},
    {0x34, 0x3f},  {0x37, 0x3f},  {0x00, 0x00},
    {0x51, 0xC2}, {0x52, 0x00}, {0x53, 0x28}, {0x54, 0x28},
    {0x3D, 0x01}, {0x56, 0x80}, {0x5E, 0x80},

    pls checkout our config of registers

    thanks

    Click here to play this audio clip

  • 0 in reply to cary he
    TI__Mastermind 22950 points

    Hello Cary,

    I see that you are unmuting the Left PGA but do not see the Right PGA unmuted (Register 0x3C). Please unmute this and write 0x32 to match the Left ADC. 

    Let me know if this helps. 


    Regards,

    Aaron