CDCE913: Start up problem

Kuramochi Tadahiko

Guru 28715 points

Part Number: CDCE913
Other Parts Discussed in Thread: CLOCKPRO

Hi,

My customer says that the CDCE913 has start up problem before.

(Because I had not supported them at the time, I do not know the problem directly.)

The symptom is unstable oscillation.

Occurrence condition of the symptom are that

1. What SSC is on.

2. What to take over a few hundred ms until input clock supplied(they use FPGA to supply) after power supplied.

Does TI recognize the problem?

If yes, has this problem been already improved?

Best Regards,

Kuramochi

over 5 years ago

0 Shawn Han over 5 years ago

TI__Genius 9920 points

Which one is earlier?
Input clock or power supply for CDCE913

0 Kuramochi Tadahiko over 5 years ago in reply to Shawn Han

Guru 28715 points

Han-san,

Thank you for your reply.
Power supply is earlier.

Best Regards,
Kuramochi

0 Shawn Han over 5 years ago in reply to Kuramochi Tadahiko

TI__Genius 9920 points

When reference is get ready, PLL would enter locking mode, locking is not locked, so output should be not stable.
After PLL locked, output becomes stable.

0 Kuramochi Tadahiko over 5 years ago in reply to Shawn Han

Guru 28715 points

Han-san,

Thank you for your reply.

What is relationship during your explanation and the problem my customer is saying?

Best regards,
Kuramochi

0 Shawn Han over 5 years ago in reply to Kuramochi Tadahiko

TI__Genius 9920 points

Hi Kuramochi,
I answered a reason for unstable output.
Looks I didn't understand your customer's problem. Could you clarify the problems in your 1st post?

"The symptom is unstable oscillation.
Occurrence condition of the symptom are that
1. What (When ?) SSC is on.
2. What ( ?) to take over a few hundred ms until input clock supplied(they use FPGA to supply) after power supplied."

Is that meaning when SSC is OFF, the unstable oscillation (output) would not happen?

Regards,
Shawn

0 Kuramochi Tadahiko over 5 years ago in reply to Shawn Han

Guru 28715 points

Shawn-san,

>Is that meaning when SSC is OFF, the unstable oscillation (output) would not happen?

Yes, your understanding is correct.

Best Regards,
Kuramochi

0 Alan O over 5 years ago in reply to Kuramochi Tadahiko

TI__Mastermind 32575 points

SSC is intentional phase modulation when it is enabled, so the output clock phase will appear unstable (like jitter) but the average frequency over time will be correct as it is configured. Did they use ClockPro to generate the configuration settings? How are they observing the "unstable behavior" (test equipment & setup)?

The SCC modulation is dependent on the VCO frequency. See the attached SSC frequency modulation calculator workseet.
e2e.ti.com/.../4137.CDCE9xx_5F00_SSC_5F00_Fmod_5F00_Calculator.xls

Alan

0 Kuramochi Tadahiko over 5 years ago in reply to Alan O

Guru 28715 points

Alan-san,

Thank you for your reply.
I'll check it.

Best Regards,
Kuramochi

0 Kuramochi Tadahiko over 5 years ago in reply to Alan O

Guru 28715 points

Alan-san,

Thank you for your help.
I'll check them.

Best Regards,
Kuramochi

0 Dean Banerjee over 5 years ago in reply to Kuramochi Tadahiko

TI__Mastermind 27581 points

Kuramochi-san,

OK, we will await your response.

Regards,
Dean

Clock & timing

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CDCE913: Start up problem