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LMX2595: Mismatch in critical noise model parameter and phase noise graphs
Part Number: LMX2595
This is a question regarding the OSC input power requirements for the best noise performance of the LMX2595.
In a previous post you mentioned that you limited the +13 dBm output from your Wenzel OCXO to +10 dBm, which is 2 Vpp into 50 ohms, which is the maximum allowed power for the OSC input according to the data sheet. I have 2 options in my design. In the first the input power is 8 dBm, in the second it's 9.6 dBm - both from a 100 MHz OCXO. Obviously the higher power (higher slew rate) is better but for other reasons I would prefer only supplying 8 dBm.
The question is, will there be a significant degradation in the output noise if only 8 dBm is used? Alternatively, does TI have a 'Added Jitter (fs) vs. OSC Input Slew Rate (V/ns)' plot or data for the LMX2595?
As an aside, I'll be using the dual LMX2595 trick (as described in TIDA-01346) to lower the output noise. In that design TI uses a resistive divider (6 dB loss) to split the input OSC signal for the dual LMX's. However, they also do not populate the shunt 51 ohm resistors at the OSCINP pins (R15 and R19), so the divider is essentially seeing an open. Was that done to boost the voltage as seen by the LMX OSC input pin? Can you please explain the reasoning there? I am planning to use a packaged Wilkinson divider (Mini-Circuits LRPS-2-1 with 3.3 dB loss @ 100 MHz) to split the input OCXO signal between the two devices, and I will have 50 ohm shunt resistors at the OSCINP pins.
For OSCin power, if the 8dBm and 9.6dBm are both sine waves (no limiter), then there will be no much difference.
About OSCin matching, Dean's opinion is that at 100MHz, the wavelength is 3 meters. For short traces, the standing wave won't cause trouble, and yes he did this to boost the voltage level sensed by OSCin pins.
Consider the 3-wire interface. An input voltage wave V is injected into the OSCin port. At the interconnect point, V sees 50Ohm for both branches and each branch gets V/2. Assume the OSCin pin is open, then the reflection coefficient is +1, so V+ and V- are equal and they add in phase. The total voltage at OCSin_P or OSCin_N is V+ + V- = V, and the full voltage level is restored. After that, everything is reflected back and no power is consumed, the overall reflection coefficient at the interconnect point has a magnitude of 1. But what matters is that the OSCin pins can sense the full voltage level.
In order not to cause any trouble, impedance matching is still recommended.
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