Part Number: LMK04832
We have clock source with frequency 122.88-125MHz and with ultra low phase noise on 20Hz to 1kHz offsets (circa 20Hz@<-100dBc/Hz, 100Hz@<-135dBc/Hz, 1kHz<-157dBc/Hz).
We are looking for solution of clock distribution of this source where outputs phase noise on the specified offsets are degraded as low as possible - ideally by 3dB max.
The solution should be JESD204B compliant. The minimum of number of outputs is 14 (4 clk/sysref pairs for ADC, 3 clk/sysref pairs for FPGA (jitter is no care)).
We are gonna measure this clock source with LMK04832EVM in distributed mode but I don't think we will achieve desired performace (according to datasheet).
Can you please recommend a device or combination of devices suitable for this job?
Thanks and regards
The LMK04832 is our only JESD compliant buffer/divider that we have for now and it does have the right number of outputs.
We don't have a lot of phase noise in distribution mode data for close-in in distribution mode. For LVPECL2.0, PLLatinum Sim predicts -160 dBc for 122.88 MHz carrier. But this is the noise floor, so at these low offsets, you could be impacted by the flicker noise.
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