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LMK04828BEVM: LMK04828 configuration in external VCO mode

Rock Su
Intellectual 2220 points
Part Number: LMK04828BEVM
Other Parts Discussed in Thread: LMK04828

Dear colleague,

Our customer has below concerns:

1. When using external VCO mode (J6), after loading the file lmk_config_external_clock. CFG, both PLL1 and PLL2 lock status lights are off. Is PLL not working or external VCO mode is not using PLL?  Doesn't the high-speed sampling clock output to ADC require octave?

2. If PLL is not used, does the external input clock source need high frequency? But I see that the input range of Fin in the datasheet is 0.001~750MHz, so how to understand it.

Best Regards,

Rock Su

  • 0
    TI__Mastermind 29010 points

    Hello Rock Su,

    1. I'm not sure to what you are referring with the file "lmk_config_external_clock", but it sounds like they want to operate with the Fin input. If the Fin is used as an external VCO, which PLL2 includes in the loop, then make sure the signal from CPout2 is connected to the tuning voltage input of the VCO, and that the VCO signal is connected to Fin. By default, we do not include an external VCO on the LMK04828BEVM.

      On the other hand, if the customer wants to use Fin as an input signal and distribute it through LMK04828 dividers and outputs, PLL1 and PLL2 are not used in this configuration. As for the high-speed sampling clock for the ADC, in many cases the ADC has an internal clock multiplier, and can accept lower frequency clock signals.
    2. Generally, if the PLL is not used, the external clock signal should be higher frequency. From the datasheet:

      The 750 MHz input frequency limit is only for 0-delay mode with external feedback, or for CLKin inputs which are divided down through the PLL1 R divider. Fin frequency can go up to 3100 MHz for normal PLL2 operation or for distribution mode (with PLLs off).

    Regards,