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LMX2594: high spurious when not in integer mode

J. H. 1
Prodigy 155 points
Part Number: LMX2594
Other Parts Discussed in Thread: TIDA-01410

Hi,

on my (selfmade) testboard for the LMX2594 I measured a big difference in spurious for integer vs. non-integer mode:

Non-integer mode:

Integer mode:

Here you can finde the settings in TICS Pro (non-integer mode):

The goal is to produce an output frequency of 8.244 GHz. How can we reduce the spurious for this frequency?

Thank you very much in advance.

Best regards
Joachim

  • 0
    Prodigy 155 points

    In the meantime I found out that switchting off VCO_Phase_Sync drastically improves the situation:

    My initial question still applies, as we want to use two phase-synced oscillators later on.

    Joachim

  • 0 in reply to J. H. 1
    TI__Genius 11900 points

    Hello Joachim,

    Please increase your MASH_ORDER to a third order modulator this will distribute the power of the spurs across the spectrum.

    Also note that you might have to adjust other settings in the PLL such as the PFD_DLY_SEL which will be marked in yellow or red.

    Finally, you can use the PLLATINUMSIM-SW tool for PN/spur simulations.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 155 points

    Hi Vibhu,

    thank you for your reply. Increasing the modulaton order does improve the spurs.

    While testing, another issue occured:

    On our board we have two PLLs, similar to TIDA-01410. When both PLLs are powered and running sometimes the waveform looks, as expeced, like in the first picture. When presing FCAL_EN in  TICS Pro sometimes the waveform stays like in the first pictures and sometimes the output looks like shown in the second picture. The output signal looks the same for both PLLs, so both are affected by the problem. Do you have any idea what is going on there? Pressing FCAL_EN a couple of times, usually helps to get the waveform back to normal. The PLLs are programmed simultaneously.

    When both PLLs are powered and only one PLL is programmed the problem does not occur.

    Thanks

    Joachim

  • 0 in reply to J. H. 1
    TI__Guru* 81710 points

    Hi Joachim,

    Are both PLLs running at the same frequency and when you run FCAL_EN, are you calibrating them at the same time?

    Looks to me that each PLL is having interference with each other. 

    My suggestion is to at least power down one of the PLL's output while programming the other PLL in order to reduce interference. 

  • 0 in reply to Noel Fung
    Prodigy 155 points

    Hi Noel,

    both PLLs have exactly the same settings and are calibrated at the same time.

    I found out that when I reduce the power of the reference oscillator, the issue is much less likely to occur.

    With an ref. osc. power of 8 dBm at the PLL input the issue occurs approx. every second time I calibrate. When I reduce the power to 0 dBm it is very hard to replicate the issue.

    When only one PLL is running and calibrated the issue does not occur.

    Thanks
    Joachim

  • 0 in reply to J. H. 1
    Prodigy 155 points

    Our board is very similar to TIDA-01410. Do you know if such an issue exists with TIDA-01410?

  • 0 in reply to J. H. 1
    TI__Genius 11900 points

    Hello Joachim,

    Have  you tried Noel's suggestion to powerdown one of the PLLs while calibrating the other to reduce interference? Your results with the  reference oscillator, suggest the same. Looks like when the power is higher the interference is also more prominent.

    I am not aware of a similar problem on the TIDA board.

    Thanks,

    Vibhu

  • 0 in reply to Vibhu Vanjari
    Prodigy 155 points

    Hi,

    yes, it works when only one PLL is powered. Do you have an idea what might causes the issue? Especially since there is seems to be no problem with the TIDA board.

    Best regards
    Joachim

  • 0 in reply to J. H. 1
    TI__Guru* 81710 points

    Hi Joachim,

    We don't know what may be the root cause, we don't have the board to debug.

    You mentioned that the problem is gone with a smaller input reference clock signal, can you live with this input level? 

    Can this issue be avoided by proper programming sequence? For example, program the synthesizer once at a time?