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LMK03328: operation availability

Part Number: LMK03328

Team,

Would you advise that 

My customer inputs 27MHz and 148MHz to PRI and SEC.

When the frame rate is 50P, the clock supplied to the LMK03328 is input with 27MHz of DUTY6:5 created by dividing 11 by 148.5MHz and 148.5MHz, but this is operating without problems.

At 59P, 148.35MHz is divided by 11, and it is further modulated by 1000/1001 to generate 27MHz, but at this time it does not work well.
The input is 148.35MHz and 27MHz which is modulated by dividing this by 11.

Does the LMK03328 have a PLL that does not work well with a clock modulated in this way?

Also, I want to find the register setting value that operates only in 148MHz

system without using 27MHz. Since WEBENCH is not supported, can I design the register value

with PLLATINUM SIM-SW?

Thanks

Best regards,

Shidara

  • Hi Shidara,

    Sorry I didn't understand the question. What frequency cannot be generated by LMK03328? There's a wizard for LMK03328 in Ticspro (https://www.ti.com/tool/TICSPRO-SW) where you can set the frequencies and program registers.

    Regards,
    Hao

  • Hi Hao-san

    Thanks for your advice.

    Input CLK are 148.35MHz and 27MHz.

    Output CLK is 148.35MHz.

    PLL Lock status is OK. Are there any register which shows the status?

    The customer is using the product which designed by another designer, then detailed register setting can not be 

    done back-annotated to the tool.

    Since the jitter cleaner is used, I don't think it is through merely.

    Any advice should be highly appreciated.

    Thanks

    Best regards,

    Shidara

  • Hi Shidara-san,

    Lock status can be seen on the two status pins, as well as bits LOL1 and LOL2, where LOL is short for Loss of Lock.

    Register content can be read back by clicking "read all registers" on the tool bar. That way you can see what registers have been set.

    Regards,
    Hao