Team,
Would you advise that
My customer inputs 27MHz and 148MHz to PRI and SEC.
When the frame rate is 50P, the clock supplied to the LMK03328 is input with 27MHz of DUTY6:5 created by dividing 11 by 148.5MHz and 148.5MHz, but this is operating without problems.
At 59P, 148.35MHz is divided by 11, and it is further modulated by 1000/1001 to generate 27MHz, but at this time it does not work well.
The input is 148.35MHz and 27MHz which is modulated by dividing this by 11.
Does the LMK03328 have a PLL that does not work well with a clock modulated in this way?
Also, I want to find the register setting value that operates only in 148MHz
system without using 27MHz. Since WEBENCH is not supported, can I design the register value
with PLLATINUM SIM-SW?
Thanks
Best regards,
Shidara