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Part Number: LMK05318
Our design requirements are in the attachment.
Two 25MHz 3.3V LVCMOS input clcok, three 25MHz 3.3V LVCMOS output and one 10MHz 3.3V LVCMOS output.
All clocks need to meet SyncE (G.8262) spec.
What is clock solution applicable for this design req? I feel LMK05318 is not OK for the req.
Could you help to recommend it?
This frequency plan can be generated by LMK05318 with no problem. LMK05318 is also G.8262 compliant.
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In reply to Hao Z:
The LMK05318 output[3:0] just support differential, output[7:4] just support 1.8V LVCMOS.
But we need 3.3V LVCMOS output..
Does TI have suitable level shift IC so that stll meet G.8262 compliant ?
In reply to wenxing zheng:
I see your concern. Yes you can use a clock buffer with low additive jitter such as LMK00105.
Thank your suggestion.
Now our SWer don't know how to program LMK05318 by I2C.
For example,our input is 19.2MHz,AC-couple and output5=10MHz LVCMOS.
We don't find the related I2C register address and the register discription in the datasheet.
First of all please use the latest wizard in Ticspro: https://www.ti.com/tool/TICSPRO-SW
Under "select device" -> network synchronizers, there's LMK05318. It is more recommended to use the LMK05318B wizard and select "backward compatible", because it is easier to use.
There's a separate programming manual for the device: https://www.ti.com/lit/ug/snau237a/snau237a.pdf?ts=1594025879128&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FLMK05318
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