This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: LMK03318
I would like to use the LMK03318 in our design and I have a few questions:
SECREF/PRIMREF connectivity: the input signal to the PLL is differential (LVPECL input).
In the data sheet the pins above state to have internal capacitors for AC couple mode.
Also Figure 45. Differential Input Buffer Termination Options on Primary and Secondary Reference demonstrate the above.
But on Table 4. Input Buffer Configuration Matrix on Primary and/or Secondary Reference, the statement for LVPECL IO standard is to use external capacitors.
(Also in the LMK03318 EVB there are external capacitors) hence as I understand it is mandatory to use the external capacitors for AC couple mode?
Also Figure 52. AC-Coupling LMK03318 Inputs With LVPECL Signal (Internal Biasing Enabled) demonstrate it.
Hence the best way (please approve) is to implement the connectivity as in the EVB (JP16 to GND).
SECREF: the input is GXO-E31L oscillator
An additional question is regarding the GPIO pin configurations:
The use is HW_SW_CTRL = 0 (soft pin mode).
GPIO0 need to be connected to VDD_DIG (Normal output driver/divider operation as configured)
GPIO1 is the I2C address lower bits.
GPIO[3:2]: the defaults of the EEPROM are not as I need and I will need either to program it before first use or via registers write
And this is the question I have - when they are floating the register defaults are loaded.
Is there a recommended way (fast and secure) to program the PLL ?
GPIO[3:2] are a select for 1 of 6 EEPROM pages, is the page definition is according to register R8[6:4] PINMODE_SW Register[GPIO32_SW_MODE]?
GPIO4 pin: Frequency margining enable how to configure it?.
GPIO5 pin : Frequency margining offset select, how to configure it?
Starting with the first question, what is the input signal that's going into primary/secondary reference? AC-coupled needs to provide external capacitors and internal biasing, DC-coupled no need for external capacitor, vcm/biasing is provided by the external clock. EVB was designed for AC-coupling. Here are the relevant notes from datasheet section 10.4.2:
I'm not sure if I understand the 2nd question... I would recommend using ticspro software to generate the configuration that you need and from there loading those registers into the device and issuing a reset. Once you have confirmed the configuration is as you need, you can program the EEPROM of the device (to whichever page of your choosing) and the device would be configured in that manner upon every subsequent power up as long as it's in EEPROM mode and the page that was programmed is selected.
Next question, are you asking if R8 readback will tell you the EEPROM page that is being selecting in the current bootup? GPIO [3:2] are the only pins that need to be set to determine the page of the EEPROM. R8 will show you the page in accordance to those settings, whether GPIO[3:2] is high, low, or floating. There's nothing that needs to be set for R8, it is a readback only.
Do you need frequency marginning for your configuration? If not, you don't need to do anything with these pins.
Thanks and regards, Amin
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Amin Eshraghi:
For the first question, I asked - yes the inputs to the PLL are AC coupled (LVPECL IO standard) , external capacitors are in the
design as required.
GPIO[3:2] are EEPROM page select, hence by hard wire I can set the page they are loaded from.
Regarding GPIO[5:4]: as I understand they are only for TXTAL setting.
If the secondary is not connected to XTAL, but to an oscillator - so as I understand GPIO[5:4] have no meaning?
If so, what is the recommended way for GPIO[5:4]?
N.C or GND/Vdd?
In reply to Omer Kvitel:
Yes, they increase the internal load capacitance for the crystal input to fine tune the frequency.
The pins can be left floating if frequency marginning is not needed.
Thanks and regards,
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.