Part Number: LMX2595
I have observed 30dB degradation in phase noise in our board compared to EVM output.
Below is the EVM output
And below is the output from our board(probed:so amplitude may not be actual)
What could be the reason for such high noise around the carrier? Reference clock is clean having more that 70 dBc delta for the same setting.
Could you describe a bit more what is the difference in setup between the EVM and your board? I cannot make any guess simply looking into these two plots.
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In reply to Noel Fung:
I have verified by giving SPI lines from EVM to my board but still the same issue, this i have done to locate whether programming is issue or hardware implementation is the issue.
There is no difference between EVM and my board except component placement and manufacturer(all capacitors are from Murata)
Description of my board:
6Layer PCB. RO4350B 10mil laminate between Layer1(RF components layer) and Layer2(RF ground). L3 is power plane. L4 is digital plane, L5 is ground, L6 is discrete components +ground
Clock is 40 MHz from CDCLVP1102RGTT differential clock driver. Tried with 100MHz clock as well.
Below is the schematics
Let me know if you need any other details.
In reply to Allamaprabhu B:
You should leave the unused RFoutB pins floating, if you still want to 50Ω shunt the pins, AC-couple is recommended.
R82 is not needed.
Not sure, but please try AC-couple the buffer output to LMX. That is, add two more DC-block capacitors on the left side of R97.
Did you measure the buffer output signal, does its phase noise look good?
Could you also try use the buffer output as the reference clock for the EVM?
For experiment, I have connected the EVM 100 MHz clock to our board, then phase noise got improved. On the other way round, 100 MHz from our board buffer output connected to EVM then phase noise degrades. So concluded that the reference clock we are using to feed to LMX have poor phase noise.
Please clarify me,
In SNAU219A document, a note given below the reference oscillator requirement table as "A noise source 10 dB down from the PLL noise will contribute to raise the noise by 0.4 dB" means here noise source refers to reference clock right?
10 dB down is for example, in figure 3 of 6.7 section in LMX2595 data sheet, at 10 KHz offset -105 dBc/Hz(approx), subtracting 10 dB to this means reference clock should have phase noise -115 dBc/Hz at 10 KHz offset. If this is so then PLL noise will degrade by 0.4 dB, that is -105dBc/Hz-0.4= -104.6 dBc/Hz. Is it correct?
Both are correct.
Thank you very much Noel for the support.
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