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LMK04832: Measuring the Loop Bandwidth and Phase Margin of PLL2

Paul Opsahl
Prodigy 40 points
Part Number: LMK04832
Other Parts Discussed in Thread: PLLATINUMSIM-SW,

I am trying to understand why there is a direct connection between the PFD and VCO that is internal to the device. I do understand the external filter being only shunt elements to ground, but this configuration does not allow for measuring the open loop gain and phase margin with a Bode box. How would TI verify the gain/phase response of PLL2?

  • 0
    TI__Mastermind 29010 points

    Hi Paul,

    We have a tool, PLLatinum Sim (PLLATINUMSIM-SW) which allows for estimation of the gain and phase margin based on characterization of a few external PLL parameters (1/f, PLL FOM, VCO open loop noise, output buffer floor). By analyzing the transfer function, we can calculate the predicted gain and phase margins, and match it to a simulated phase noise plot. If we then go into the lab and measure the phase noise with the given conditions, we should see that the phase noise offsets match closely to our simulated results. If the results significantly diverged from simulation, it stands to reason that the gain and phase margins are incorrect, and either the PLL is not properly configured or there is an unmodeled nuance to the PLL behavior. I have found that for all but very extreme cases (no loop filter, phase detector beyond allowed range, etc), PLL2 behavior matches PLLatinum Sim predictions quite closely. 

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 40 points

    I am aware of and have used the PLLatinum SIM tool in this application of the LMK04832. I used the LPF elements recommended by the application, and found a disparity between the simulated noise and the measured noise. Verification of the gain/phase-margin is also a normal step in the synthesizer development process, so that was just another reason to measure it. It appears that we are unable to do this test on the LMK04832. Maybe need to make some changes and see where this goes.